core: Add alternate reset address

An external signal can control whether the core will start
executing at the standard or the alternate reset address.

This will be used when litedram is initialized by microwatt
itself, to route the reset to the built-in init code secondary
block RAM.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
pull/170/head
Benjamin Herrenschmidt 4 years ago
parent 982cf166dd
commit 6853d22203

@ -10,12 +10,17 @@ entity core is
generic (
SIM : boolean := false;
DISABLE_FLATTEN : boolean := false;
EX1_BYPASS : boolean := true
EX1_BYPASS : boolean := true;
ALT_RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0')
);
port (
clk : in std_logic;
rst : in std_logic;
clk : in std_ulogic;
rst : in std_ulogic;

-- Alternate reset (0xffff0000) for use by DRAM init fw
alt_reset : in std_ulogic;

-- Wishbone interface
wishbone_insn_in : in wishbone_slave_out;
wishbone_insn_out : out wishbone_master_out;

@ -125,11 +130,13 @@ begin

fetch1_0: entity work.fetch1
generic map (
RESET_ADDRESS => (others => '0')
RESET_ADDRESS => (others => '0'),
ALT_RESET_ADDRESS => ALT_RESET_ADDRESS
)
port map (
clk => clk,
rst => core_rst,
alt_reset_in => alt_reset,
stall_in => fetch1_stall_in,
flush_in => flush,
stop_in => dbg_core_stop,

@ -27,7 +27,8 @@ begin
rst => rst,
system_clk => clk,
uart0_rxd => '0',
uart0_txd => open
uart0_txd => open,
alt_reset => '0'
);

clk_process: process

@ -7,7 +7,8 @@ use work.common.all;

entity fetch1 is
generic(
RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0')
RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0');
ALT_RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0')
);
port(
clk : in std_ulogic;
@ -17,6 +18,7 @@ entity fetch1 is
stall_in : in std_ulogic;
flush_in : in std_ulogic;
stop_in : in std_ulogic;
alt_reset_in : in std_ulogic;

-- redirect from execution unit
e_in : in Execute1ToFetch1Type;
@ -60,7 +62,11 @@ begin
v_int := r_int;

if rst = '1' then
v.nia := RESET_ADDRESS;
if alt_reset_in = '1' then
v.nia := ALT_RESET_ADDRESS;
else
v.nia := RESET_ADDRESS;
end if;
v_int.stop_state := RUNNING;
elsif e_in.redirect = '1' then
v.nia := e_in.redirect_nia;

@ -27,7 +27,8 @@ entity soc is

-- UART0 signals:
uart0_txd : out std_ulogic;
uart0_rxd : in std_ulogic
uart0_rxd : in std_ulogic;
alt_reset : in std_ulogic
);
end entity soc;

@ -89,11 +90,13 @@ begin
processor: entity work.core
generic map(
SIM => SIM,
DISABLE_FLATTEN => DISABLE_FLATTEN_CORE
DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
ALT_RESET_ADDRESS => (15 downto 0 => '0', others => '1')
)
port map(
clk => system_clk,
rst => rst,
alt_reset => alt_reset,
wishbone_insn_in => wishbone_icore_in,
wishbone_insn_out => wishbone_icore_out,
wishbone_data_in => wishbone_dcore_in,

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