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The current dcache will not update the PLRU on a cache miss which is later satisfied during the reload process. Thus subsequent misses will potentially evict the same cache line. The same issue happens with dcbz which are treated more/less as load misses. This fixes it by triggering a PLRU update when r1.choose_victim, which is set on a miss for one cycle to snapshot the PLRU output. This means we will update the PLRU on the same cycle as we capture its output, which is fine (the new value will be visible on the next cycle). That way, a "miss" will result in a PLRU update to reflect that the entry being refilled is actually used (and will be used to serve subsequent load operations from the same cache line while being refilled). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>pull/411/head

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