cores
/
microwatt
mirror of https://github.com/antonblanchard/microwatt
3
1
Fork 1
Code Issues Projects Releases Wiki Activity

Merge pull request #442 from paulusmack/fpu

Browse Source 
This reworks the FPU logic to try and get closer to the point where the
big state machine could be converted into microcode. This means that
as far as possible the state machine should just set control lines, ideally
with as little conditional logic in each state as possible, and that anything
that is considered data should be manipulated outside of the state
machine. This also improves architecture compliance in the area of
exception handling, and alleviates some critical paths.
pull/444/head
Paul Mackerras 7 months ago committed by GitHub
parent c5abe3c0a9 3268ef717c
commit 7e544c1fb8
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
4 changed files with 1168 additions and 960 deletions
Show Stats Download Patch File Download Diff File

4
decode1.vhdl
Unescape Escape View File

@ -151,8 +151,8 @@ architecture behaviour of decode1 is
INSN_fabs => (FPU, FPU, OP_FP_MOVE, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fadd => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fadds => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fcfid => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fcfids => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fcfid => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', '0', NONE),
INSN_fcfids => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0', '0', NONE),
INSN_fcfidu => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fcfidus => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fcmpo => (FPU, FPU, OP_FP_CMP, FRA, FRB, NONE, NONE, NONE, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),

2053
fpu.vhdl
View File

File diff suppressed because it is too large Load Diff

71
tests/fpu/fpu.c
Unescape Escape View File

@ -1496,34 +1496,105 @@ struct fmavals {
unsigned long nfma;
unsigned long nfms;
} fmavals[] = {
/* +0 * +0 +- +0 -> +0, +0, -0, -0 */
{ 0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
0x0000000000000000, 0x0000000000000000, 0x8000000000000000, 0x8000000000000000 },
/* +0 * NaNC +- +0 -> NaNC, NaNC, NaNC, NaNC */
{ 0x0000000000000000, 0x7ffc000000000000, 0x0000000000000000,
0x7ffc000000000000, 0x7ffc000000000000, 0x7ffc000000000000, 0x7ffc000000000000 },
/* +0 * NaNC +- NaNB -> NaNB, NaNB, NaNB, NaNB */
{ 0x0000000000000000, 0x7ffc000000000000, 0x7ffb000000000000,
0x7ffb000000000000, 0x7ffb000000000000, 0x7ffb000000000000, 0x7ffb000000000000 },
/* NaNA * NaNC +- NaNB -> NaNA, NaNA, NaNA, NaNA */
{ 0x7ffa000000000000, 0x7ffc000000000000, 0x7ffb000000000000,
0x7ffa000000000000, 0x7ffa000000000000, 0x7ffa000000000000, 0x7ffa000000000000 },
/* +1.0 * -0 +- +finite B -> +B, -B, -B, +B */
{ 0x3ff0000000000000, 0x8000000000000000, 0x678123456789abcd,
0x678123456789abcd, 0xe78123456789abcd, 0xe78123456789abcd, 0x678123456789abcd },
/* +1.0 * -1.0 +- (B = +3.818e+190) -> +B, -B, -B, +B */
{ 0x3ff0000000000000, 0xbff0000000000000, 0x678123456789abcd,
0x678123456789abcd, 0xe78123456789abcd, 0xe78123456789abcd, 0x678123456789abcd },
/* +inf * -1.0 +- +finite B -> -inf, -inf, +inf, +inf */
{ 0x7ff0000000000000, 0xbff0000000000000, 0x678123456789abcd,
0xfff0000000000000, 0xfff0000000000000, 0x7ff0000000000000, 0x7ff0000000000000 },
/* +inf * +0 +- +finite B -> NaNQ, NaNQ, NaNQ, NaNQ */
{ 0x7ff0000000000000, 0x0000000000000000, 0x678123456789abcd,
0x7ff8000000000000, 0x7ff8000000000000, 0x7ff8000000000000, 0x7ff8000000000000 },
/* +1.0 * +1.0 +- 1.00000012 -> +2.00000012, +1.2e-7, -2.00000012, -1.2e-7 */
{ 0x3ff0000000000000, 0x3ff0000000000000, 0x3ff0000020000000,
0x4000000010000000, 0xbe80000000000000, 0xc000000010000000, 0x3e80000000000000 },
/* +(1 + 2^-52) * +(1 + 2^-52) +- +1.0 -> +(2 + 2^-51), +2^-51, -(2 + 2^-51), -2^-51 */
{ 0x3ff0000000000001, 0x3ff0000000000001, 0x3ff0000000000000,
0x4000000000000001, 0x3cc0000000000000, 0xc000000000000001, 0xbcc0000000000000 },
/* +(1 + 3*2^-52) * +(1 + 2^-51) +- +1.0 -> +(2 + 2^-50), +5 * 2^-52 + 2^-101, -, - */
{ 0x3ff0000000000003, 0x3ff0000000000002, 0x3ff0000000000000,
0x4000000000000002, 0x3cd4000000000002, 0xc000000000000002, 0xbcd4000000000002 },
/* +2.443e-77 * 2.828 +- 6.909e-77 -> -1.402e-93, +1.382e-76, +1.402e-93, -1.382e-76 */
{ 0x3006a09e667f3bcc, 0x4006a09e667f3bcd, 0xb020000000000000,
0xaca765753908cd20, 0x3030000000000000, 0x2ca765753908cd20, 0xb030000000000000 },
/* +2.443e-77 * 2.828 +- 6.909e-77 -> +9.446e-93, +1.382e-76, -9.446e-93, -1.382e-76 */
{ 0x3006a09e667f3bcd, 0x4006a09e667f3bcd, 0xb020000000000000,
0x2cd3b3efbf5e2229, 0x3030000000000000, 0xacd3b3efbf5e2229, 0xb030000000000000 },
/* +2.443e-77 * 2.828 +- -1.1055e-75 -> -1.0364e-75, +1.1746e-75, +1.0364e-75, -1.1746e-75 */
{ 0x3006a09e667f3bcc, 0x4006a09e667f3bcd, 0xb060003450000000,
0xb05e0068a0000000, 0x3061003450000000, 0x305e0068a0000000, 0xb061003450000000 },
/* +2 * +3 +- 3 -> +9, +3, -9, -3 */
{ 0x4000000000000000, 0x4008000000000000, 0x4008000000000000,
0x4022000000000000, 0x4008000000000000, 0xc022000000000000, 0xc008000000000000 },
/* +2 * +3 +- 5 -> +11, +1, -11, -1 */
{ 0x4000000000000000, 0x4008000000000000, 0x4014000000000000,
0x4026000000000000, 0x3ff0000000000000, 0xc026000000000000, 0xbff0000000000000 },
/* +2 * +3 +- 7 -> +13, -1, -13, +1 */
{ 0x4000000000000000, 0x4008000000000000, 0x401c000000000000,
0x402a000000000000, 0xbff0000000000000, 0xc02a000000000000, 0x3ff0000000000000 },
/* +2 * +3 +- 9 -> +15, -3, -15, +3 */
{ 0x4000000000000000, 0x4008000000000000, 0x4022000000000000,
0x402e000000000000, 0xc008000000000000, 0xc02e000000000000, 0x4008000000000000 },
/* +2 * +3 +- -3 -> +3, +9, -3, -9 */
{ 0x4000000000000000, 0x4008000000000000, 0xc008000000000000,
0x4008000000000000, 0x4022000000000000, 0xc008000000000000, 0xc022000000000000 },
/* +2 * +3 +- -5 -> +1, +11, -1, -11 */
{ 0x4000000000000000, 0x4008000000000000, 0xc014000000000000,
0x3ff0000000000000, 0x4026000000000000, 0xbff0000000000000, 0xc026000000000000 },
/* +2 * +3 +- -7 -> -1, +13, +1, -13 */
{ 0x4000000000000000, 0x4008000000000000, 0xc01c000000000000,
0xbff0000000000000, 0x402a000000000000, 0x3ff0000000000000, 0xc02a000000000000 },
/* +2 * +3 +- -9 -> -3, +15, +3, -15 */
{ 0x4000000000000000, 0x4008000000000000, 0xc022000000000000,
0xc008000000000000, 0x402e000000000000, 0x4008000000000000, 0xc02e000000000000 },
/* +2 * -3 +- 3 -> -3, -9, +3, +9 */
{ 0x4000000000000000, 0xc008000000000000, 0x4008000000000000,
0xc008000000000000, 0xc022000000000000, 0x4008000000000000, 0x4022000000000000 },
/* +2 * -3 +- 5 -> -1, -11, +1, +11 */
{ 0x4000000000000000, 0xc008000000000000, 0x4014000000000000,
0xbff0000000000000, 0xc026000000000000, 0x3ff0000000000000, 0x4026000000000000 },
/* +2 * -3 +- 7 -> +1, -13, -1, +13 */
{ 0x4000000000000000, 0xc008000000000000, 0x401c000000000000,
0x3ff0000000000000, 0xc02a000000000000, 0xbff0000000000000, 0x402a000000000000 },
/* +2 * -3 +- 9 -> +3, -15, -3, +15 */
{ 0x4000000000000000, 0xc008000000000000, 0x4022000000000000,
0x4008000000000000, 0xc02e000000000000, 0xc008000000000000, 0x402e000000000000 },
/* -2 * +3 +- -3 -> -9, -3, +9, +3 */
{ 0xc000000000000000, 0x4008000000000000, 0xc008000000000000,
0xc022000000000000, 0xc008000000000000, 0x4022000000000000, 0x4008000000000000 },
/* -2 * +3 +- -5 -> -11, -1, +11, +1 */
{ 0xc000000000000000, 0x4008000000000000, 0xc014000000000000,
0xc026000000000000, 0xbff0000000000000, 0x4026000000000000, 0x3ff0000000000000 },
/* -2 * +3 +- -7 -> -13, +1, +13, -1 */
{ 0xc000000000000000, 0x4008000000000000, 0xc01c000000000000,
0xc02a000000000000, 0x3ff0000000000000, 0x402a000000000000, 0xbff0000000000000 },
/* -2 * +3 +- -9 -> -15, +3, +15, -3 */
{ 0xc000000000000000, 0x4008000000000000, 0xc022000000000000,
0xc02e000000000000, 0x4008000000000000, 0x402e000000000000, 0xc008000000000000 },
/* -2 * +3 +- +0 -> -6, -6, +6, +6 */
{ 0xc000000000000000, 0x4008000000000000, 0x0000000000000000,
0xc018000000000000, 0xc018000000000000, 0x4018000000000000, 0x4018000000000000 },
/* +2 * -3 +- -0 -> -6, -6, +6, +6 */
{ 0x4000000000000000, 0xc008000000000000, 0x8000000000000000,
0xc018000000000000, 0xc018000000000000, 0x4018000000000000, 0x4018000000000000 },
/* 2^-1026 * (1.5 * 2^1023) +- -0 -> (1.5 * 2^-3), ditto, -ditto, -ditto */
{ 0x0001000000000000, 0x7fe8000000000000, 0x8000000000000000,
0x3fc8000000000000, 0x3fc8000000000000, 0xbfc8000000000000, 0xbfc8000000000000 },
};

int test23(long arg)

BIN
tests/test_fpu.bin
View File

Binary file not shown.
Write Preview
Loading…
Cancel
Save