liteeth: Regenerate from current upstream litex

Some signals have changed names: "eth_" has been dropped from the
names of the MII/GMII/RGMII signals.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

fpga/top-arty.vhdl

@@ -484,18 +484,18 @@ begin
         component liteeth_core port (
             sys_clock           : in std_ulogic;
             sys_reset           : in std_ulogic;
-            mii_eth_clocks_tx   : in std_ulogic;
-            mii_eth_clocks_rx   : in std_ulogic;
-            mii_eth_rst_n       : out std_ulogic;
-            mii_eth_mdio        : in std_ulogic;
-            mii_eth_mdc         : out std_ulogic;
-            mii_eth_rx_dv       : in std_ulogic;
-            mii_eth_rx_er       : in std_ulogic;
-            mii_eth_rx_data     : in std_ulogic_vector(3 downto 0);
-            mii_eth_tx_en       : out std_ulogic;
-            mii_eth_tx_data     : out std_ulogic_vector(3 downto 0);
-            mii_eth_col         : in std_ulogic;
-            mii_eth_crs         : in std_ulogic;
+            mii_clocks_tx       : in std_ulogic;
+            mii_clocks_rx       : in std_ulogic;
+            mii_rst_n           : out std_ulogic;
+            mii_mdio            : in std_ulogic;
+            mii_mdc             : out std_ulogic;
+            mii_rx_dv           : in std_ulogic;
+            mii_rx_er           : in std_ulogic;
+            mii_rx_data         : in std_ulogic_vector(3 downto 0);
+            mii_tx_en           : out std_ulogic;
+            mii_tx_data         : out std_ulogic_vector(3 downto 0);
+            mii_col             : in std_ulogic;
+            mii_crs             : in std_ulogic;
             wishbone_adr        : in std_ulogic_vector(29 downto 0);
             wishbone_dat_w      : in std_ulogic_vector(31 downto 0);
             wishbone_dat_r      : out std_ulogic_vector(31 downto 0);
@@ -569,18 +569,18 @@ begin
             port map(
                 sys_clock         => system_clk,
                 sys_reset         => periph_rst,
-                mii_eth_clocks_tx => eth_clocks_tx,
-                mii_eth_clocks_rx => eth_clocks_rx,
-                mii_eth_rst_n     => eth_rst_n,
-                mii_eth_mdio      => eth_mdio,
-                mii_eth_mdc       => eth_mdc,
-                mii_eth_rx_dv     => eth_rx_dv,
-                mii_eth_rx_er     => eth_rx_er,
-                mii_eth_rx_data   => eth_rx_data,
-                mii_eth_tx_en     => eth_tx_en,
-                mii_eth_tx_data   => eth_tx_data,
-                mii_eth_col       => eth_col,
-                mii_eth_crs       => eth_crs,
+                mii_clocks_tx     => eth_clocks_tx,
+                mii_clocks_rx     => eth_clocks_rx,
+                mii_rst_n         => eth_rst_n,
+                mii_mdio          => eth_mdio,
+                mii_mdc           => eth_mdc,
+                mii_rx_dv         => eth_rx_dv,
+                mii_rx_er         => eth_rx_er,
+                mii_rx_data       => eth_rx_data,
+                mii_tx_en         => eth_tx_en,
+                mii_tx_data       => eth_tx_data,
+                mii_col           => eth_col,
+                mii_crs           => eth_crs,
                 wishbone_adr      => wb_eth_adr,
                 wishbone_dat_w    => wb_ext_io_in.dat,
                 wishbone_dat_r    => wb_eth_out.dat,

fpga/top-nexys-video.vhdl

@@ -384,16 +384,16 @@ begin
         component liteeth_core port (
             sys_clock           : in std_ulogic;
             sys_reset           : in std_ulogic;
-            rgmii_eth_clocks_tx : out std_ulogic;
-            rgmii_eth_clocks_rx : in std_ulogic;
-            rgmii_eth_rst_n     : out std_ulogic;
-            rgmii_eth_int_n     : in std_ulogic;
-            rgmii_eth_mdio      : inout std_ulogic;
-            rgmii_eth_mdc       : out std_ulogic;
-            rgmii_eth_rx_ctl    : in std_ulogic;
-            rgmii_eth_rx_data   : in std_ulogic_vector(3 downto 0);
-            rgmii_eth_tx_ctl    : out std_ulogic;
-            rgmii_eth_tx_data   : out std_ulogic_vector(3 downto 0);
+            rgmii_clocks_tx     : out std_ulogic;
+            rgmii_clocks_rx     : in std_ulogic;
+            rgmii_rst_n         : out std_ulogic;
+            rgmii_int_n         : in std_ulogic;
+            rgmii_mdio          : inout std_ulogic;
+            rgmii_mdc           : out std_ulogic;
+            rgmii_rx_ctl        : in std_ulogic;
+            rgmii_rx_data       : in std_ulogic_vector(3 downto 0);
+            rgmii_tx_ctl        : out std_ulogic;
+            rgmii_tx_data       : out std_ulogic_vector(3 downto 0);
             wishbone_adr        : in std_ulogic_vector(29 downto 0);
             wishbone_dat_w      : in std_ulogic_vector(31 downto 0);
             wishbone_dat_r      : out std_ulogic_vector(31 downto 0);
@@ -417,16 +417,16 @@ begin
             port map(
                 sys_clock           => system_clk,
                 sys_reset           => soc_rst,
-                rgmii_eth_clocks_tx => eth_clocks_tx,
-                rgmii_eth_clocks_rx => eth_clocks_rx,
-                rgmii_eth_rst_n     => eth_rst_n,
-                rgmii_eth_int_n     => eth_int_n,
-                rgmii_eth_mdio      => eth_mdio,
-                rgmii_eth_mdc       => eth_mdc,
-                rgmii_eth_rx_ctl    => eth_rx_ctl,
-                rgmii_eth_rx_data   => eth_rx_data,
-                rgmii_eth_tx_ctl    => eth_tx_ctl,
-                rgmii_eth_tx_data   => eth_tx_data,
+                rgmii_clocks_tx     => eth_clocks_tx,
+                rgmii_clocks_rx     => eth_clocks_rx,
+                rgmii_rst_n         => eth_rst_n,
+                rgmii_int_n         => eth_int_n,
+                rgmii_mdio          => eth_mdio,
+                rgmii_mdc           => eth_mdc,
+                rgmii_rx_ctl        => eth_rx_ctl,
+                rgmii_rx_data       => eth_rx_data,
+                rgmii_tx_ctl        => eth_tx_ctl,
+                rgmii_tx_data       => eth_tx_data,
                 wishbone_adr        => wb_eth_adr,
                 wishbone_dat_w      => wb_ext_io_in.dat,
                 wishbone_dat_r      => wb_eth_out.dat,

fpga/top-wukong-v2.vhdl

@@ -380,20 +380,20 @@ begin
         component liteeth_core port (
             sys_clock           : in std_ulogic;
             sys_reset           : in std_ulogic;
-            gmii_eth_clocks_tx  : in std_ulogic;
-            gmii_eth_clocks_gtx : out std_ulogic;
-            gmii_eth_clocks_rx  : in std_ulogic;
-            gmii_eth_rst_n      : out std_ulogic;
-            gmii_eth_mdio       : inout std_ulogic;
-            gmii_eth_mdc        : out std_ulogic;
-            gmii_eth_rx_dv      : in std_ulogic;
-            gmii_eth_rx_er      : in std_ulogic;
-            gmii_eth_rx_data    : in std_ulogic_vector(7 downto 0);
-            gmii_eth_tx_en      : out std_ulogic;
-            gmii_eth_tx_er      : out std_ulogic;
-            gmii_eth_tx_data    : out std_ulogic_vector(7 downto 0);
-            gmii_eth_col        : in std_ulogic;
-            gmii_eth_crs        : in std_ulogic;
+            gmii_clocks_tx      : in std_ulogic;
+            gmii_clocks_gtx     : out std_ulogic;
+            gmii_clocks_rx      : in std_ulogic;
+            gmii_rst_n          : out std_ulogic;
+            gmii_mdio           : inout std_ulogic;
+            gmii_mdc            : out std_ulogic;
+            gmii_rx_dv          : in std_ulogic;
+            gmii_rx_er          : in std_ulogic;
+            gmii_rx_data        : in std_ulogic_vector(7 downto 0);
+            gmii_tx_en          : out std_ulogic;
+            gmii_tx_er          : out std_ulogic;
+            gmii_tx_data        : out std_ulogic_vector(7 downto 0);
+            gmii_col            : in std_ulogic;
+            gmii_crs            : in std_ulogic;
             wishbone_adr        : in std_ulogic_vector(29 downto 0);
             wishbone_dat_w      : in std_ulogic_vector(31 downto 0);
             wishbone_dat_r      : out std_ulogic_vector(31 downto 0);
@@ -420,20 +420,20 @@ begin
             port map(
                 sys_clock           => system_clk,
                 sys_reset           => soc_rst,
-                gmii_eth_clocks_tx  => eth_clocks_tx,
-                gmii_eth_clocks_gtx => eth_clocks_gtx,
-                gmii_eth_clocks_rx  => eth_clocks_rx,
-                gmii_eth_rst_n      => eth_rst_n,
-                gmii_eth_mdio       => eth_mdio,
-                gmii_eth_mdc        => eth_mdc,
-                gmii_eth_rx_dv      => eth_rx_dv,
-                gmii_eth_rx_er      => eth_rx_er,
-                gmii_eth_rx_data    => eth_rx_data,
-                gmii_eth_tx_en      => eth_tx_en,
-                gmii_eth_tx_er      => eth_tx_er,
-                gmii_eth_tx_data    => eth_tx_data,
-                gmii_eth_col        => eth_col,
-                gmii_eth_crs        => eth_crs,
+                gmii_clocks_tx      => eth_clocks_tx,
+                gmii_clocks_gtx     => eth_clocks_gtx,
+                gmii_clocks_rx      => eth_clocks_rx,
+                gmii_rst_n          => eth_rst_n,
+                gmii_mdio           => eth_mdio,
+                gmii_mdc            => eth_mdc,
+                gmii_rx_dv          => eth_rx_dv,
+                gmii_rx_er          => eth_rx_er,
+                gmii_rx_data        => eth_rx_data,
+                gmii_tx_en          => eth_tx_en,
+                gmii_tx_er          => eth_tx_er,
+                gmii_tx_data        => eth_tx_data,
+                gmii_col            => eth_col,
+                gmii_crs            => eth_crs,
                 wishbone_adr        => wb_eth_adr,
                 wishbone_dat_w      => wb_ext_io_in.dat,
                 wishbone_dat_r      => wb_eth_out.dat,