Add eSim NGHDL integration support for Microwatt
Signed-off-by: KirupaNithi <kirupanithi789@gmail.com>pull/468/head
KirupaNithi
6 days ago
parent
efd0571b5f
commit
99934896c5
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#!/bin/bash
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# ==========================================================
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# Compile Microwatt + NGHDL wrapper
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# Full simulation-safe flow with all C helper linking
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# ==========================================================
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set -e
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ESIM_DIR="esim"
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WORK_DIR="esim/ghdl_work"
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rm -rf "$WORK_DIR"
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mkdir -p "$WORK_DIR"
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echo "=============================================="
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echo " Step 0: Build required C helper objects"
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echo "=============================================="
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cc -O3 -Wall -c -o sim_vhpi_c.o sim_vhpi_c.c
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cc -O3 -Wall -c -o sim_console_c.o sim_console_c.c
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cc -O3 -Wall -c -o sim_bram_helpers_c.o sim_bram_helpers_c.c
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echo "=============================================="
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echo " Step 1: Compile Microwatt + wrapper"
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echo "=============================================="
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ghdl -c --std=08 --workdir="$WORK_DIR" \
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-Wl,sim_vhpi_c.o \
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-Wl,sim_console_c.o \
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-Wl,sim_bram_helpers_c.o \
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decode_types.vhdl \
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common.vhdl \
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wishbone_types.vhdl \
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fetch1.vhdl \
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utils.vhdl \
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plrufn.vhdl \
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cache_ram.vhdl \
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icache.vhdl \
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predecode.vhdl \
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decode1.vhdl \
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helpers.vhdl \
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insn_helpers.vhdl \
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control.vhdl \
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decode2.vhdl \
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register_file.vhdl \
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cr_file.vhdl \
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crhelpers.vhdl \
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ppc_fx_insns.vhdl \
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rotator.vhdl \
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logical.vhdl \
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countbits.vhdl \
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multiply.vhdl \
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multiply-32s.vhdl \
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divider.vhdl \
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execute1.vhdl \
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loadstore1.vhdl \
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mmu.vhdl \
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dcache.vhdl \
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writeback.vhdl \
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core_debug.vhdl \
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core.vhdl \
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fpu.vhdl \
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pmu.vhdl \
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bitsort.vhdl \
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wishbone_arbiter.vhdl \
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wishbone_bram_wrapper.vhdl \
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sync_fifo.vhdl \
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wishbone_debug_master.vhdl \
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xics.vhdl \
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git.vhdl \
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syscon.vhdl \
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gpio.vhdl \
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dmi_dtm_dummy.vhdl \
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soc.vhdl \
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spi_rxtx.vhdl \
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spi_flash_ctrl.vhdl \
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sim_console.vhdl \
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sim_pp_uart.vhdl \
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sim_bram_helpers.vhdl \
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sim_bram.vhdl \
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sim_16550_uart.vhdl \
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foreign_random.vhdl \
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glibc_random.vhdl \
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glibc_random_helpers.vhdl \
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"$ESIM_DIR/microwatt_cosim.vhdl" \
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-e microwatt_cosim
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echo "=============================================="
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echo " SUCCESS"
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echo "=============================================="
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echo "Microwatt NGHDL wrapper compiled successfully"
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echo "GHDL work directory: $WORK_DIR"
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@ -0,0 +1,131 @@
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-- =========================================================
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-- Microwatt eSim / NGHDL ultra-minimal wrapper
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-- Parser-safe scalar version
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-- =========================================================
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity microwatt_cosim is
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port (
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clk : in std_logic;
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rst : in std_logic;
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uart_tx : out std_logic
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);
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end entity microwatt_cosim;
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architecture rtl of microwatt_cosim is
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--------------------------------------------------------------------
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-- Internal SoC signals
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--------------------------------------------------------------------
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signal run_s : std_ulogic;
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signal uart_tx_s : std_ulogic;
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signal gpio_out_s : std_ulogic_vector(31 downto 0);
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signal gpio_dir_s : std_ulogic_vector(31 downto 0);
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signal gpio_in_s : std_ulogic_vector(31 downto 0) := (others => '0');
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--------------------------------------------------------------------
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-- Dummy DRAM Wishbone signals
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--------------------------------------------------------------------
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signal wb_dram_in_s : wishbone_master_out;
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signal wb_dram_out_s : wishbone_slave_out := wishbone_slave_out_init;
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--------------------------------------------------------------------
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-- Dummy external IO signals
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--------------------------------------------------------------------
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signal wb_ext_io_in_s : wb_io_master_out;
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signal wb_ext_io_out_s : wb_io_slave_out := wb_io_slave_out_init;
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signal wb_ext_is_dram_csr_s : std_ulogic;
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signal wb_ext_is_dram_init_s : std_ulogic;
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signal wb_ext_is_eth_s : std_ulogic;
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signal wb_ext_is_sdcard_s : std_ulogic;
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signal wb_ext_is_lcd_s : std_ulogic;
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--------------------------------------------------------------------
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-- Dummy DMA signals
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--------------------------------------------------------------------
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signal wishbone_dma_in_s : wb_io_slave_out;
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signal wishbone_dma_out_s : wb_io_master_out := wb_io_master_out_init;
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begin
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--------------------------------------------------------------------
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-- Microwatt SoC instance
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--------------------------------------------------------------------
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soc_inst: entity work.soc
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generic map (
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MEMORY_SIZE => 524288,
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RAM_INIT_FILE => "",
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CLK_FREQ => 100000000,
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SIM => true,
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NCPUS => 1,
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HAS_FPU => true,
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HAS_BTC => true,
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DISABLE_FLATTEN_CORE => false,
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HAS_DRAM => false,
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HAS_SPI_FLASH => false,
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HAS_LITEETH => false,
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HAS_UART1 => false,
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HAS_SD_CARD => false,
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HAS_SD_CARD2 => false,
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HAS_LCD => false,
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HAS_GPIO => false,
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NGPIO => 32
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)
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port map (
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rst => rst,
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system_clk => clk,
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run_out => run_s,
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run_outs => open,
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wb_dram_in => wb_dram_in_s,
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wb_dram_out => wb_dram_out_s,
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wb_ext_io_in => wb_ext_io_in_s,
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wb_ext_io_out => wb_ext_io_out_s,
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wb_ext_is_dram_csr => wb_ext_is_dram_csr_s,
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wb_ext_is_dram_init => wb_ext_is_dram_init_s,
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wb_ext_is_eth => wb_ext_is_eth_s,
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wb_ext_is_sdcard => wb_ext_is_sdcard_s,
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wb_ext_is_lcd => wb_ext_is_lcd_s,
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wishbone_dma_in => wishbone_dma_in_s,
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wishbone_dma_out => wishbone_dma_out_s,
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ext_irq_eth => '0',
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ext_irq_sdcard => '0',
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ext_irq_sdcard2 => '0',
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uart0_txd => uart_tx_s,
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uart0_rxd => '1',
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uart1_txd => open,
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uart1_rxd => '0',
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spi_flash_sck => open,
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spi_flash_cs_n => open,
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spi_flash_sdat_o => open,
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spi_flash_sdat_oe => open,
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spi_flash_sdat_i => (others => '1'),
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gpio_out => gpio_out_s,
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gpio_dir => gpio_dir_s,
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gpio_in => gpio_in_s,
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sw_soc_reset => open
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);
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--------------------------------------------------------------------
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-- Scalar output
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--------------------------------------------------------------------
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uart_tx <= std_logic(uart_tx_s);
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end architecture rtl;
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