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@ -92,8 +92,7 @@ architecture behaviour of execute1 is
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mult_32s : std_ulogic;
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write_fscr : std_ulogic;
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write_ic : std_ulogic;
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write_hfscr : std_ulogic;
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write_hic : std_ulogic;
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write_lpcr : std_ulogic;
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write_heir : std_ulogic;
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set_heir : std_ulogic;
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write_ctrl : std_ulogic;
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@ -212,6 +211,7 @@ architecture behaviour of execute1 is
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signal valid_in : std_ulogic;
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signal ctrl: ctrl_t := ctrl_t_init;
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signal ctrl_tmp: ctrl_t := ctrl_t_init;
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signal dec_sign: std_ulogic;
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signal rotator_result: std_ulogic_vector(63 downto 0);
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signal rotator_carry: std_ulogic;
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signal logical_result: std_ulogic_vector(63 downto 0);
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@ -224,6 +224,7 @@ architecture behaviour of execute1 is
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signal spr_result: std_ulogic_vector(63 downto 0);
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signal next_nia : std_ulogic_vector(63 downto 0);
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signal s1_sel : std_ulogic_vector(2 downto 0);
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signal log_spr_data : std_ulogic_vector(63 downto 0);
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signal carry_32 : std_ulogic;
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signal carry_64 : std_ulogic;
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@ -410,15 +411,17 @@ architecture behaviour of execute1 is
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return ret;
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end;
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function assemble_hfscr(c: ctrl_t) return std_ulogic_vector is
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function assemble_lpcr(c: ctrl_t) return std_ulogic_vector is
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variable ret : std_ulogic_vector(63 downto 0);
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begin
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ret := (others => '0');
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ret(59 downto 56) := c.hfscr_ic;
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ret(HFSCR_PREFIX) := c.hfscr_pref;
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ret(HFSCR_TAR) := c.hfscr_tar;
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ret(HFSCR_DSCR) := c.hfscr_dscr;
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ret(HFSCR_FP) := c.hfscr_fp;
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ret(LPCR_HAIL) := c.lpcr_hail;
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ret(LPCR_UPRT) := '1';
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ret(LPCR_HR) := '1';
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ret(LPCR_LD) := c.lpcr_ld;
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ret(LPCR_HEIC) := c.lpcr_heic;
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ret(LPCR_LPES) := c.lpcr_lpes;
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ret(LPCR_HVICE) := c.lpcr_hvice;
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return ret;
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end;
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@ -457,6 +460,15 @@ architecture behaviour of execute1 is
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return ret;
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end;
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function assemble_dec(c: ctrl_t) return std_ulogic_vector is
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begin
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if c.lpcr_ld = '1' then
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return c.dec;
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else
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return 32x"0" & c.dec(31 downto 0);
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end if;
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end;
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-- Tell vivado to keep the hierarchy for the random module so that the
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-- net names in the xdc file match.
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attribute keep_hierarchy : string;
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@ -596,6 +608,8 @@ begin
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tb_next <= thi & tlo;
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end process;
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dec_sign <= (ctrl.dec(63) and ctrl.lpcr_ld) or (ctrl.dec(31) and not ctrl.lpcr_ld);
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dbg_ctrl_out <= ctrl;
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log_rd_addr <= ex2.log_addr_spr;
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@ -796,8 +810,8 @@ begin
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case dbg_spr_addr(3 downto 0) is
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when SPRSEL_FSCR =>
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dbg_spr_data <= assemble_fscr(ctrl);
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when SPRSEL_HFSCR =>
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dbg_spr_data <= assemble_hfscr(ctrl);
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when SPRSEL_LPCR =>
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dbg_spr_data <= assemble_lpcr(ctrl);
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when SPRSEL_HEIR =>
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dbg_spr_data <= ctrl.heir;
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when SPRSEL_CFAR =>
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@ -1189,6 +1203,7 @@ begin
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v.e.redir_mode := ex1.msr(MSR_IR) & not ex1.msr(MSR_PR) &
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not ex1.msr(MSR_LE) & not ex1.msr(MSR_SF);
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v.e.intr_vec := 16#700#;
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v.e.alt_intr := ctrl.lpcr_hail and ex1.msr(MSR_IR) and ex1.msr(MSR_DR);
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v.e.mode_32bit := not ex1.msr(MSR_SF);
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v.e.instr_tag := e_in.instr_tag;
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v.e.last_nia := e_in.nia;
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@ -1387,8 +1402,10 @@ begin
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slow_op := '1';
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if e_in.spr_select.ispmu = '0' then
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case e_in.spr_select.sel is
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when SPRSEL_LOGD =>
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v.se.inc_loga := '1';
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when SPRSEL_LOGR =>
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if e_in.insn(16) = '0' then
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v.se.inc_loga := '1';
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end if;
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when others =>
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end case;
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v.res2_sel := "10";
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@ -1451,14 +1468,14 @@ begin
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v.se.write_xerlow := '1';
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when SPRSEL_DEC =>
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v.se.write_dec := '1';
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when SPRSEL_LOGA =>
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when SPRSEL_LOGR =>
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v.se.write_loga := '1';
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when SPRSEL_CFAR =>
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v.se.write_cfar := '1';
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when SPRSEL_FSCR =>
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v.se.write_fscr := '1';
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when SPRSEL_HFSCR =>
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v.se.write_hfscr := '1';
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when SPRSEL_LPCR =>
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v.se.write_lpcr := '1';
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when SPRSEL_HEIR =>
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v.se.write_heir := '1';
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when SPRSEL_CTRL =>
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@ -1548,22 +1565,15 @@ begin
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end case;
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if ex1.msr(MSR_PR) = '1' and e_in.prefixed = '1' and
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(ctrl.hfscr_pref = '0' or ctrl.fscr_pref = '0') then
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-- [Hypervisor] facility unavailable for prefixed instructions,
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ctrl.fscr_pref = '0' then
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-- Facility unavailable for prefixed instructions,
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-- which has higher priority than the alignment interrupt for
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-- misaligned prefixed instructions, which has higher priority than
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-- other [hypervisor] facility unavailable interrupts (e.g. for
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-- plfs with HFSCR[FP] = 0).
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-- other facility unavailable interrupts.
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v.exception := '1';
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v.ic := x"b";
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if ctrl.hfscr_pref = '0' then
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v.e.hv_intr := '1';
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v.e.intr_vec := 16#f80#;
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v.se.write_hic := '1';
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else
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v.e.intr_vec := 16#f60#;
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v.se.write_ic := '1';
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end if;
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v.e.intr_vec := 16#f60#;
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v.se.write_ic := '1';
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elsif misaligned = '1' then
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-- generate an alignment interrupt
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@ -1608,41 +1618,20 @@ begin
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v.se.write_ic := '1';
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elsif ex1.msr(MSR_PR) = '1' and e_in.uses_tar = '1' and
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(ctrl.hfscr_tar = '0' or ctrl.fscr_tar = '0') then
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-- [Hypervisor] facility unavailable for TAR access
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ctrl.fscr_tar = '0' then
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-- Facility unavailable for TAR access
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v.exception := '1';
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v.ic := x"8";
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if ctrl.hfscr_tar = '0' then
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v.e.hv_intr := '1';
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v.e.intr_vec := 16#f80#;
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v.se.write_hic := '1';
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else
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v.e.intr_vec := 16#f60#;
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v.se.write_ic := '1';
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end if;
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v.e.intr_vec := 16#f60#;
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v.se.write_ic := '1';
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elsif ex1.msr(MSR_PR) = '1' and e_in.uses_dscr = '1' and
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(ctrl.hfscr_dscr = '0' or ctrl.fscr_dscr = '0') then
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-- [Hypervisor] facility unavailable for DSCR access
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ctrl.fscr_dscr = '0' then
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-- Facility unavailable for DSCR access
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v.exception := '1';
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v.ic := x"2";
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if ctrl.hfscr_dscr = '0' then
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v.e.hv_intr := '1';
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v.e.intr_vec := 16#f80#;
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v.se.write_hic := '1';
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else
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v.e.intr_vec := 16#f60#;
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v.se.write_ic := '1';
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end if;
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elsif HAS_FPU and ex1.msr(MSR_PR) = '1' and e_in.fac = FPU and
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ctrl.hfscr_fp = '0' then
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-- Hypervisor facility unavailable for FP instructions
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v.exception := '1';
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v.ic := x"0";
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v.e.hv_intr := '1';
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v.e.intr_vec := 16#f80#;
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v.se.write_hic := '1';
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v.e.intr_vec := 16#f60#;
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v.se.write_ic := '1';
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elsif HAS_FPU and ex1.msr(MSR_FP) = '0' and e_in.fac = FPU then
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-- generate a floating-point unavailable interrupt
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@ -1705,7 +1694,8 @@ begin
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v.busy := '0';
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bypass_valid := actions.bypass_valid;
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irq_valid := ex1.msr(MSR_EE) and (pmu_to_x.intr or ctrl.dec(63) or ext_irq_in);
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irq_valid := ex1.msr(MSR_EE) and (pmu_to_x.intr or dec_sign or
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(ext_irq_in and not ctrl.lpcr_heic));
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if valid_in = '1' then
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v.prev_op := e_in.insn_type;
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@ -1747,14 +1737,14 @@ begin
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if pmu_to_x.intr = '1' then
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v.e.intr_vec := 16#f00#;
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report "IRQ valid: PMU";
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elsif ctrl.dec(63) = '1' then
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elsif dec_sign = '1' then
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v.e.intr_vec := 16#900#;
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report "IRQ valid: DEC";
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elsif ext_irq_in = '1' then
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v.e.intr_vec := 16#500#;
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report "IRQ valid: External";
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v.ext_interrupt := '1';
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v.e.hv_intr := '1';
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v.e.hv_intr := not ctrl.lpcr_lpes;
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end if;
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v.e.srr1 := (others => '0');
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exception := '1';
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@ -1968,23 +1958,25 @@ begin
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end process;
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-- Slow SPR read mux
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log_spr_data <= (log_wr_addr & ex2.log_addr_spr) when ex1.insn(16) = '0'
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else log_rd_data;
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with ex1.spr_select.sel select spr_result <=
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timebase when SPRSEL_TB,
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32x"0" & timebase(63 downto 32) when SPRSEL_TBU,
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ctrl.dec when SPRSEL_DEC,
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assemble_dec(ctrl) when SPRSEL_DEC,
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32x"0" & PVR_MICROWATT when SPRSEL_PVR,
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log_wr_addr & ex2.log_addr_spr when SPRSEL_LOGA,
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log_rd_data when SPRSEL_LOGD,
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log_spr_data when SPRSEL_LOGR,
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ctrl.cfar when SPRSEL_CFAR,
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assemble_fscr(ctrl) when SPRSEL_FSCR,
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assemble_hfscr(ctrl) when SPRSEL_HFSCR,
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assemble_lpcr(ctrl) when SPRSEL_LPCR,
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ctrl.heir when SPRSEL_HEIR,
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assemble_ctrl(ctrl, ex1.msr(MSR_PR)) when SPRSEL_CTRL,
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39x"0" & ctrl.dscr when SPRSEL_DSCR,
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56x"0" & std_ulogic_vector(to_unsigned(CPU_INDEX, 8)) when SPRSEL_PIR,
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ctrl.ciabr when SPRSEL_CIABR,
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assemble_dexcr(ctrl, ex1.insn) when SPRSEL_DEXCR,
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assemble_xer(ex1.e.xerc, ctrl.xer_low) when others;
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assemble_xer(ex1.e.xerc, ctrl.xer_low) when SPRSEL_XER,
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64x"0" when others;
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stage2_stall <= l_in.l2stall or fp_in.f2stall;
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@ -2127,15 +2119,6 @@ begin
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v.log_addr_spr := std_ulogic_vector(unsigned(ex2.log_addr_spr) + 1);
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end if;
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x_to_pmu.mtspr <= ex1.se.write_pmuspr;
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if ex1.se.write_hfscr = '1' then
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ctrl_tmp.hfscr_ic <= ex1.e.write_data(59 downto 56);
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ctrl_tmp.hfscr_pref <= ex1.e.write_data(HFSCR_PREFIX);
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ctrl_tmp.hfscr_tar <= ex1.e.write_data(HFSCR_TAR);
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ctrl_tmp.hfscr_dscr <= ex1.e.write_data(HFSCR_DSCR);
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ctrl_tmp.hfscr_fp <= ex1.e.write_data(HFSCR_FP);
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elsif ex1.se.write_hic = '1' then
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ctrl_tmp.hfscr_ic <= ex1.ic;
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end if;
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|
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if ex1.se.write_fscr = '1' then
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|
|
ctrl_tmp.fscr_ic <= ex1.e.write_data(59 downto 56);
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|
|
ctrl_tmp.fscr_pref <= ex1.e.write_data(FSCR_PREFIX);
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@ -2145,6 +2128,13 @@ begin
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|
elsif ex1.se.write_ic = '1' then
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ctrl_tmp.fscr_ic <= ex1.ic;
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end if;
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|
|
if ex1.se.write_lpcr = '1' then
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ctrl_tmp.lpcr_hail <= ex1.e.write_data(LPCR_HAIL);
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ctrl_tmp.lpcr_ld <= ex1.e.write_data(LPCR_LD);
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ctrl_tmp.lpcr_heic <= ex1.e.write_data(LPCR_HEIC);
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ctrl_tmp.lpcr_lpes <= ex1.e.write_data(LPCR_LPES);
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ctrl_tmp.lpcr_hvice <= ex1.e.write_data(LPCR_HVICE);
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end if;
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if ex1.se.write_heir = '1' then
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ctrl_tmp.heir <= ex1.e.write_data;
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elsif ex1.se.set_heir = '1' then
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@ -2173,7 +2163,7 @@ begin
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-- pending exceptions clear any wait state
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-- ex1.fp_exception_next is not tested because it is not possible to
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-- get into wait state with a pending FP exception.
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irq_exc := pmu_to_x.intr or ctrl.dec(63) or ext_irq_in;
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irq_exc := pmu_to_x.intr or dec_sign or ext_irq_in;
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if ex1.trace_next = '1' or irq_exc = '1' or interrupt_in.intr = '1' then
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ctrl_tmp.wait_state <= '0';
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end if;
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@ -2186,11 +2176,13 @@ begin
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ctrl_tmp.msr(MSR_FP) <= '0';
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ctrl_tmp.msr(MSR_FE0) <= '0';
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ctrl_tmp.msr(MSR_FE1) <= '0';
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ctrl_tmp.msr(MSR_IR) <= '0';
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ctrl_tmp.msr(MSR_DR) <= '0';
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ctrl_tmp.msr(MSR_IR) <= interrupt_in.alt_int;
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ctrl_tmp.msr(MSR_DR) <= interrupt_in.alt_int;
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ctrl_tmp.msr(MSR_LE) <= '1';
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if interrupt_in.scv_int = '0' then
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ctrl_tmp.msr(MSR_EE) <= '0';
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end if;
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if interrupt_in.scv_int = '0' and interrupt_in.hv_intr = '0' then
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ctrl_tmp.msr(MSR_RI) <= '0';
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end if;
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end if;
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@ -2214,7 +2206,6 @@ begin
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-- update outputs
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e_out <= ex2.e;
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e_out.msr <= msr_copy(ctrl.msr);
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run_out <= ctrl.run;
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terminate_out <= ex2.se.terminate;
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