Add dummy clock generator

pull/2/head
Olof Kindgren 5 years ago
parent 37fe8b954c
commit b5bccc4c13

@ -0,0 +1,20 @@
library ieee;
use ieee.std_logic_1164.all;

entity clock_generator is
port (
clk : in std_logic;
resetn : in std_logic;
system_clk : out std_logic;
locked : out std_logic);

end entity clock_generator;

architecture bypass of clock_generator is

begin

locked <= not resetn;
system_clk <= clk;

end architecture bypass;
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