litesdcard: Regenerate verilog code with buffer direction controls

This regenerates the verilog code from upstream litex plus a patch to generate outputs from the litesdcard module for controlling bidirectional buffers between the FPGA and SD card. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
1 month ago · c1f23e7417
parent 264e609fd4
commit c1f23e7417
2 changed files with 8334 additions and 7609 deletions
--- a/litesdcard/generated/lattice.48e6/litesdcard_core.v
+++ b/litesdcard/generated/lattice.48e6/litesdcard_core.v
--- a/litesdcard/generated/xilinx.100e6/litesdcard_core.v
+++ b/litesdcard/generated/xilinx.100e6/litesdcard_core.v