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@ -549,8 +549,8 @@ begin
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-- Mask write selects with do_write since BRAM doesn't always
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-- have a global write-enable (Vivado generates TDP instead
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-- of SDP when using one, thus doubling cache BRAM usage).
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for i in 0 to ROW_SIZE-1 loop
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wr_sel_m(i) <= wr_sel(i) and do_write;
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for j in 0 to ROW_SIZE-1 loop
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wr_sel_m(j) <= wr_sel(j) and do_write;
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end loop;
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if TRACE and rising_edge(system_clk) then
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@ -796,7 +796,9 @@ begin
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-- Store signals (hard wired for 64-bit wishbone at the moment)
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req_wsl <= wb_req.adr(WB_WSEL_BITS-1 downto 0);
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for i in 0 to WB_WORD_COUNT-1 loop
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if to_integer(unsigned(req_wsl)) = i then
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if is_X(req_wsl) then
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req_we(WBSL*(i+1)-1 downto WBSL*i) <= x"XX";
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elsif to_integer(unsigned(req_wsl)) = i then
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req_we(WBSL*(i+1)-1 downto WBSL*i) <= wb_req.sel;
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else
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req_we(WBSL*(i+1)-1 downto WBSL*i) <= x"00";
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@ -916,7 +918,9 @@ begin
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stq_sel := storeq_rd_data(WBSL+WB_WSEL_BITS-1 downto WB_WSEL_BITS);
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stq_wsl := storeq_rd_data(WB_WSEL_BITS-1 downto 0);
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for i in 0 to WB_WORD_COUNT-1 loop
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if to_integer(unsigned(stq_wsl)) = i then
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if is_X(stq_wsl) then
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user_port0_wdata_we(WBSL*(i+1)-1 downto WBSL*i) <= x"XX";
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elsif to_integer(unsigned(stq_wsl)) = i then
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user_port0_wdata_we(WBSL*(i+1)-1 downto WBSL*i) <= stq_sel;
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else
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user_port0_wdata_we(WBSL*(i+1)-1 downto WBSL*i) <= x"00";
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@ -1122,7 +1126,7 @@ begin
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component litedram_trace_stub
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end component;
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begin
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litedram_trace: litedram_trace_stub;
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litedram_trace_s: litedram_trace_stub;
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end generate;
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litedram: litedram_core
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