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@ -117,7 +117,7 @@ architecture behaviour of soc is
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-- UART0 signals:
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signal wb_uart0_in : wb_io_master_out;
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signal wb_uart0_out : wb_io_slave_out;
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signal uart_dat8 : std_ulogic_vector(7 downto 0);
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signal uart0_dat8 : std_ulogic_vector(7 downto 0);
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-- SPI Flash controller signals:
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signal wb_spiflash_in : wb_io_master_out;
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@ -571,13 +571,13 @@ begin
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irq => int_level_in(0),
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wb_adr_in => wb_uart0_in.adr(11 downto 0),
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wb_dat_in => wb_uart0_in.dat(7 downto 0),
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wb_dat_out => uart_dat8,
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wb_dat_out => uart0_dat8,
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wb_cyc_in => wb_uart0_in.cyc,
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wb_stb_in => wb_uart0_in.stb,
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wb_we_in => wb_uart0_in.we,
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wb_ack_out => wb_uart0_out.ack
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);
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wb_uart0_out.dat <= x"000000" & uart_dat8;
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wb_uart0_out.dat <= x"000000" & uart0_dat8;
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wb_uart0_out.stall <= not wb_uart0_out.ack;
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spiflash_gen: if HAS_SPI_FLASH generate
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