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Remove some FPGA style signal inits

These don't work on the ASIC flow, so remove them and initialise
them explicitly where required.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
less-fpga-init
Anton Blanchard 6 months ago committed by Anton Blanchard
parent
commit
ebdddcc402
  1. 10
      spi_flash_ctrl.vhdl
  2. 9
      spi_rxtx.vhdl

10
spi_flash_ctrl.vhdl

@ -58,7 +58,7 @@ architecture rtl of spi_flash_ctrl is @@ -58,7 +58,7 @@ architecture rtl of spi_flash_ctrl is
alias ctrl_div : std_ulogic_vector(7 downto 0) is ctrl_reg(15 downto 8);

-- Auto mode config register
signal auto_cfg_reg : std_ulogic_vector(29 downto 0) := (others => '0');
signal auto_cfg_reg : std_ulogic_vector(29 downto 0);
alias auto_cfg_cmd : std_ulogic_vector(7 downto 0) is auto_cfg_reg(7 downto 0);
alias auto_cfg_dummies : std_ulogic_vector(2 downto 0) is auto_cfg_reg(10 downto 8);
alias auto_cfg_mode : std_ulogic_vector(1 downto 0) is auto_cfg_reg(12 downto 11);
@ -126,9 +126,9 @@ architecture rtl of spi_flash_ctrl is @@ -126,9 +126,9 @@ architecture rtl of spi_flash_ctrl is
signal auto_latch_adr : std_ulogic;

-- Automatic mode latches
signal auto_data : std_ulogic_vector(wb_out.dat'left downto 0) := (others => '0');
signal auto_cnt : integer range 0 to 63 := 0;
signal auto_state : auto_state_t := AUTO_BOOT;
signal auto_data : std_ulogic_vector(wb_out.dat'left downto 0);
signal auto_cnt : integer range 0 to 63;
signal auto_state : auto_state_t;
signal auto_last_addr : std_ulogic_vector(31 downto 0);

begin
@ -351,6 +351,8 @@ begin @@ -351,6 +351,8 @@ begin
if rst = '1' then
auto_last_addr <= (others => '0');
auto_state <= AUTO_BOOT;
auto_cnt <= 0;
auto_data <= (others => '0');
else
auto_state <= auto_next;
auto_cnt <= auto_cnt_next;

9
spi_rxtx.vhdl

@ -126,10 +126,10 @@ architecture rtl of spi_rxtx is @@ -126,10 +126,10 @@ architecture rtl of spi_rxtx is
signal dat_ack_l : std_ulogic;

-- Delayed recv signal for the read machine
signal sck_recv_d : std_ulogic := '0';
signal sck_recv_d : std_ulogic;

-- Input shift register (use fifo ?)
signal ireg : std_ulogic_vector(7 downto 0) := (others => '0');
signal ireg : std_ulogic_vector(7 downto 0);

-- Bit counter
signal bit_count : std_ulogic_vector(2 downto 0);
@ -157,7 +157,7 @@ architecture rtl of spi_rxtx is @@ -157,7 +157,7 @@ architecture rtl of spi_rxtx is
end;

type state_t is (STANDBY, DATA);
signal state : state_t := STANDBY;
signal state : state_t;
begin

-- We don't support multiple data lines at this point
@ -349,6 +349,9 @@ begin @@ -349,6 +349,9 @@ begin
shift_in: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
ireg <= (others => '0');
end if;

-- Delay the receive signal to match the input latch
if state = DATA then

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