Merge pull request #80 from antonblanchard/misc

Reduce register file footprint
pull/81/head
Anton Blanchard 5 years ago committed by GitHub
commit f1ac8894b1
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@ -213,10 +213,6 @@ package common is
write_cr_data : std_ulogic_vector(31 downto 0);
end record;
constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', others => (others => '0'));

-- Would prefer not to expose this outside the register file, but ghdl
-- doesn't support external names
type regfile is array(0 to 32) of std_ulogic_vector(63 downto 0);
end common;

package body common is

@ -94,9 +94,6 @@ architecture behave of core is
-- Debug status
signal dbg_core_is_stopped: std_ulogic;

-- For sim
signal registers: regfile;

begin

core_rst <= dbg_core_rst or rst;
@ -180,12 +177,16 @@ begin
);

register_file_0: entity work.register_file
generic map (
SIM => SIM
)
port map (
clk => clk,
d_in => decode2_to_register_file,
d_out => register_file_to_decode2,
w_in => writeback_to_register_file,
registers_out => registers);
sim_dump => terminate
);

cr_file_0: entity work.cr_file
port map (
@ -277,17 +278,4 @@ begin
terminated_out => terminated_out
);

-- Dump registers if core terminates
sim_terminate_test: if SIM generate
dump_registers: process(all)
begin
if terminate = '1' then
loop_0: for i in 0 to 31 loop
report "REG " & to_hstring(registers(i));
end loop loop_0;
assert false report "end of test" severity failure;
end if;
end process;
end generate;

end behave;

@ -6,6 +6,9 @@ library work;
use work.common.all;

entity register_file is
generic (
SIM : boolean := false
);
port(
clk : in std_logic;

@ -15,11 +18,12 @@ entity register_file is
w_in : in WritebackToRegisterFileType;

-- debug
registers_out : out regfile
sim_dump : in std_ulogic
);
end entity register_file;

architecture behaviour of register_file is
type regfile is array(0 to 32) of std_ulogic_vector(63 downto 0);
signal registers : regfile := (others => (others => '0'));
begin
-- synchronous writes
@ -64,6 +68,17 @@ begin
end if;
end process register_read_0;

-- debug
registers_out <= registers;
-- Dump registers if core terminates
sim_dump_test: if SIM generate
dump_registers: process(all)
begin
if sim_dump = '1' then
loop_0: for i in 0 to 31 loop
report "REG " & to_hstring(registers(i));
end loop loop_0;
assert false report "end of test" severity failure;
end if;
end process;
end generate;

end architecture behaviour;

@ -105,7 +105,7 @@ static void open_socket(void)
fprintf(stderr, "Failed to listen to debug socket !\r\n");
goto fail;
}
fprintf(stderr, "Debug socket ready\r\n");
fprintf(stdout, "Debug socket ready\r\n");
return;
fail:
if (fd >= 0)
@ -121,7 +121,7 @@ static void check_connection(void)
cfd = accept(fd, (struct sockaddr *)&addr, &addr_len);
if (cfd < 0)
return;
fprintf(stderr, "Debug client connected !\r\n");
fprintf(stdout, "Debug client connected !\r\n");
}

void sim_jtag_read_msg(unsigned char *out_msg, unsigned char *out_size)
@ -150,7 +150,7 @@ void sim_jtag_read_msg(unsigned char *out_msg, unsigned char *out_size)
if (rc < 0)
fprintf(stderr, "Debug read error, assuming client disconnected !\r\n");
if (rc == 0)
fprintf(stderr, "Debug client disconnected !\r\n");
fprintf(stdout, "Debug client disconnected !\r\n");
if (rc <= 0) {
close(cfd);
cfd = -1;

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