Anton Blanchard
4 years ago
committed by
GitHub
commit
fcec66acf4
@ -0,0 +1,246 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library unisim;
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use unisim.vcomponents.all;
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library work;
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use work.wishbone_types.all;
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entity toplevel is
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generic (
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MEMORY_SIZE : positive := 16384;
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RAM_INIT_FILE : string := "firmware.hex";
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RESET_LOW : boolean := true;
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CLK_FREQUENCY : positive := 100000000;
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USE_LITEDRAM : boolean := false;
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DISABLE_FLATTEN_CORE : boolean := false
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);
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port(
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ext_clk : in std_ulogic;
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ext_rst : in std_ulogic;
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-- UART0 signals:
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uart_main_tx : out std_ulogic;
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uart_main_rx : in std_ulogic;
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-- DRAM UART signals (PMOD)
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uart_pmod_tx : out std_ulogic;
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uart_pmod_rx : in std_ulogic;
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uart_pmod_cts_n : in std_ulogic;
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uart_pmod_rts_n : out std_ulogic;
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-- LEDs
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led0_b : out std_ulogic;
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led0_g : out std_ulogic;
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led0_r : out std_ulogic;
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-- DRAM wires
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ddram_a : out std_ulogic_vector(13 downto 0);
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ddram_ba : out std_ulogic_vector(2 downto 0);
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ddram_ras_n : out std_ulogic;
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ddram_cas_n : out std_ulogic;
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ddram_we_n : out std_ulogic;
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ddram_cs_n : out std_ulogic;
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ddram_dm : out std_ulogic_vector(1 downto 0);
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ddram_dq : inout std_ulogic_vector(15 downto 0);
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ddram_dqs_p : inout std_ulogic_vector(1 downto 0);
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ddram_dqs_n : inout std_ulogic_vector(1 downto 0);
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ddram_clk_p : out std_ulogic;
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ddram_clk_n : out std_ulogic;
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ddram_cke : out std_ulogic;
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ddram_odt : out std_ulogic;
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ddram_reset_n : out std_ulogic
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);
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end entity toplevel;
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architecture behaviour of toplevel is
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-- Reset signals:
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signal soc_rst : std_ulogic;
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signal pll_rst : std_ulogic;
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-- Internal clock signals:
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signal system_clk : std_ulogic;
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signal system_clk_locked : std_ulogic;
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-- DRAM wishbone connection
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signal wb_dram_in : wishbone_master_out;
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signal wb_dram_out : wishbone_slave_out;
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signal wb_dram_csr : std_ulogic;
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signal wb_dram_init : std_ulogic;
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-- Control/status
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signal core_alt_reset : std_ulogic;
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-- Status LED
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signal led0_b_pwm : std_ulogic;
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signal led0_r_pwm : std_ulogic;
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signal led0_g_pwm : std_ulogic;
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-- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise
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signal pwm_counter : std_ulogic_vector(8 downto 0);
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begin
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uart_pmod_rts_n <= '0';
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-- Main SoC
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soc0: entity work.soc
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generic map(
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MEMORY_SIZE => MEMORY_SIZE,
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RAM_INIT_FILE => RAM_INIT_FILE,
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RESET_LOW => RESET_LOW,
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SIM => false,
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CLK_FREQ => CLK_FREQUENCY,
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HAS_DRAM => USE_LITEDRAM,
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DRAM_SIZE => 256 * 1024 * 1024,
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DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE
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)
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port map (
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system_clk => system_clk,
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rst => soc_rst,
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uart0_txd => uart_main_tx,
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uart0_rxd => uart_main_rx,
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wb_dram_in => wb_dram_in,
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wb_dram_out => wb_dram_out,
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wb_dram_csr => wb_dram_csr,
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wb_dram_init => wb_dram_init,
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alt_reset => core_alt_reset
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);
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nodram: if not USE_LITEDRAM generate
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signal ddram_clk_dummy : std_ulogic;
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begin
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reset_controller: entity work.soc_reset
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generic map(
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RESET_LOW => RESET_LOW
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)
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port map(
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ext_clk => ext_clk,
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pll_clk => system_clk,
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pll_locked_in => system_clk_locked,
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ext_rst_in => ext_rst,
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pll_rst_out => pll_rst,
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rst_out => soc_rst
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);
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clkgen: entity work.clock_generator
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generic map(
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CLK_INPUT_HZ => 100000000,
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CLK_OUTPUT_HZ => CLK_FREQUENCY
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)
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port map(
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ext_clk => ext_clk,
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pll_rst_in => pll_rst,
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pll_clk_out => system_clk,
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pll_locked_out => system_clk_locked
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);
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led0_b_pwm <= '1';
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led0_r_pwm <= '1';
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led0_g_pwm <= '0';
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core_alt_reset <= '0';
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-- Vivado barfs on those differential signals if left
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-- unconnected. So instanciate a diff. buffer and feed
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-- it a constant '0'.
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dummy_dram_clk: OBUFDS
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port map (
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O => ddram_clk_p,
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OB => ddram_clk_n,
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I => ddram_clk_dummy
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);
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ddram_clk_dummy <= '0';
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end generate;
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has_dram: if USE_LITEDRAM generate
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signal dram_init_done : std_ulogic;
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signal dram_init_error : std_ulogic;
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signal soc_rst_0 : std_ulogic;
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signal soc_rst_1 : std_ulogic;
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begin
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-- Eventually dig out the frequency from the generator
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-- but for now, assert it's 100Mhz
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assert CLK_FREQUENCY = 100000000;
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reset_controller: entity work.soc_reset
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generic map(
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RESET_LOW => RESET_LOW
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)
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port map(
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ext_clk => ext_clk,
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pll_clk => system_clk,
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pll_locked_in => system_clk_locked,
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ext_rst_in => ext_rst,
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pll_rst_out => pll_rst,
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rst_out => soc_rst_0
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);
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dram: entity work.litedram_wrapper
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generic map(
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DRAM_ABITS => 24,
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DRAM_ALINES => 14
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)
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port map(
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clk_in => ext_clk,
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rst => pll_rst,
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system_clk => system_clk,
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system_reset => soc_rst_1,
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core_alt_reset => core_alt_reset,
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pll_locked => system_clk_locked,
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wb_in => wb_dram_in,
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wb_out => wb_dram_out,
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wb_is_csr => wb_dram_csr,
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wb_is_init => wb_dram_init,
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serial_tx => uart_pmod_tx,
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serial_rx => uart_pmod_rx,
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init_done => dram_init_done,
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init_error => dram_init_error,
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ddram_a => ddram_a,
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ddram_ba => ddram_ba,
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ddram_ras_n => ddram_ras_n,
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ddram_cas_n => ddram_cas_n,
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ddram_we_n => ddram_we_n,
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ddram_cs_n => ddram_cs_n,
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ddram_dm => ddram_dm,
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ddram_dq => ddram_dq,
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ddram_dqs_p => ddram_dqs_p,
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ddram_dqs_n => ddram_dqs_n,
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ddram_clk_p => ddram_clk_p,
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ddram_clk_n => ddram_clk_n,
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ddram_cke => ddram_cke,
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ddram_odt => ddram_odt,
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ddram_reset_n => ddram_reset_n
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);
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led0_b_pwm <= not dram_init_done;
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led0_r_pwm <= dram_init_error;
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led0_g_pwm <= dram_init_done and not dram_init_error;
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soc_rst <= soc_rst_0 or soc_rst_1;
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end generate;
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leds_pwm : process(system_clk)
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begin
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if rising_edge(system_clk) then
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pwm_counter <= std_ulogic_vector(signed(pwm_counter) + 1);
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if pwm_counter(8 downto 4) = "00000" then
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led0_b <= led0_b_pwm;
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led0_r <= led0_r_pwm;
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led0_g <= led0_g_pwm;
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else
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led0_b <= '0';
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led0_r <= '0';
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led0_g <= '0';
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end if;
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end if;
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end process;
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end architecture behaviour;
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@ -0,0 +1,209 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library unisim;
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use unisim.vcomponents.all;
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library work;
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use work.wishbone_types.all;
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entity toplevel is
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generic (
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MEMORY_SIZE : positive := 16384;
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RAM_INIT_FILE : string := "firmware.hex";
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RESET_LOW : boolean := true;
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CLK_FREQUENCY : positive := 100000000;
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USE_LITEDRAM : boolean := false;
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DISABLE_FLATTEN_CORE : boolean := false
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);
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port(
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ext_clk : in std_ulogic;
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ext_rst : in std_ulogic;
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-- UART0 signals:
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uart_main_tx : out std_ulogic;
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uart_main_rx : in std_ulogic;
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-- LEDs
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led0 : out std_logic;
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led1 : out std_logic;
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-- DRAM wires
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ddram_a : out std_logic_vector(14 downto 0);
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ddram_ba : out std_logic_vector(2 downto 0);
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ddram_ras_n : out std_logic;
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ddram_cas_n : out std_logic;
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ddram_we_n : out std_logic;
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ddram_dm : out std_logic_vector(1 downto 0);
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ddram_dq : inout std_logic_vector(15 downto 0);
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ddram_dqs_p : inout std_logic_vector(1 downto 0);
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ddram_dqs_n : inout std_logic_vector(1 downto 0);
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ddram_clk_p : out std_logic;
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ddram_clk_n : out std_logic;
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ddram_cke : out std_logic;
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ddram_odt : out std_logic;
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ddram_reset_n : out std_logic
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);
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end entity toplevel;
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architecture behaviour of toplevel is
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-- Reset signals:
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signal soc_rst : std_ulogic;
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signal pll_rst : std_ulogic;
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-- Internal clock signals:
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signal system_clk : std_ulogic;
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signal system_clk_locked : std_ulogic;
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-- DRAM wishbone connection
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signal wb_dram_in : wishbone_master_out;
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signal wb_dram_out : wishbone_slave_out;
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signal wb_dram_csr : std_ulogic;
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signal wb_dram_init : std_ulogic;
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-- Control/status
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signal core_alt_reset : std_ulogic;
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begin
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-- Main SoC
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soc0: entity work.soc
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generic map(
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MEMORY_SIZE => MEMORY_SIZE,
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RAM_INIT_FILE => RAM_INIT_FILE,
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RESET_LOW => RESET_LOW,
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SIM => false,
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CLK_FREQ => CLK_FREQUENCY,
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HAS_DRAM => USE_LITEDRAM,
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DRAM_SIZE => 512 * 1024 * 1024,
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DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE
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)
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port map (
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system_clk => system_clk,
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rst => soc_rst,
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uart0_txd => uart_main_tx,
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uart0_rxd => uart_main_rx,
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wb_dram_in => wb_dram_in,
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wb_dram_out => wb_dram_out,
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wb_dram_csr => wb_dram_csr,
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wb_dram_init => wb_dram_init,
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alt_reset => core_alt_reset
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);
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nodram: if not USE_LITEDRAM generate
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signal ddram_clk_dummy : std_ulogic;
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begin
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reset_controller: entity work.soc_reset
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generic map(
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RESET_LOW => RESET_LOW
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)
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port map(
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ext_clk => ext_clk,
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pll_clk => system_clk,
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pll_locked_in => system_clk_locked,
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ext_rst_in => ext_rst,
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pll_rst_out => pll_rst,
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rst_out => soc_rst
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);
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clkgen: entity work.clock_generator
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generic map(
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CLK_INPUT_HZ => 100000000,
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CLK_OUTPUT_HZ => CLK_FREQUENCY
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)
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port map(
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ext_clk => ext_clk,
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pll_rst_in => pll_rst,
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pll_clk_out => system_clk,
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pll_locked_out => system_clk_locked
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);
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led0 <= '1';
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led1 <= not soc_rst;
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core_alt_reset <= '0';
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-- Vivado barfs on those differential signals if left
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-- unconnected. So instanciate a diff. buffer and feed
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-- it a constant '0'.
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dummy_dram_clk: OBUFDS
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port map (
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O => ddram_clk_p,
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OB => ddram_clk_n,
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I => ddram_clk_dummy
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);
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ddram_clk_dummy <= '0';
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end generate;
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has_dram: if USE_LITEDRAM generate
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signal dram_init_done : std_ulogic;
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signal dram_init_error : std_ulogic;
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signal soc_rst_0 : std_ulogic;
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signal soc_rst_1 : std_ulogic;
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begin
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-- Eventually dig out the frequency from the generator
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-- but for now, assert it's 100Mhz
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assert CLK_FREQUENCY = 100000000;
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reset_controller: entity work.soc_reset
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generic map(
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RESET_LOW => RESET_LOW
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)
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port map(
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ext_clk => ext_clk,
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pll_clk => system_clk,
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pll_locked_in => system_clk_locked,
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ext_rst_in => ext_rst,
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pll_rst_out => pll_rst,
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rst_out => soc_rst_0
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);
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dram: entity work.litedram_wrapper
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generic map(
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DRAM_ABITS => 25,
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DRAM_ALINES => 15
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)
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port map(
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clk_in => ext_clk,
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rst => pll_rst,
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system_clk => system_clk,
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system_reset => soc_rst_1,
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pll_locked => system_clk_locked,
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wb_in => wb_dram_in,
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wb_out => wb_dram_out,
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wb_is_csr => wb_dram_csr,
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wb_is_init => wb_dram_init,
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serial_tx => open,
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serial_rx => '0',
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init_done => dram_init_done,
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init_error => dram_init_error,
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ddram_a => ddram_a,
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ddram_ba => ddram_ba,
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ddram_ras_n => ddram_ras_n,
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ddram_cas_n => ddram_cas_n,
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ddram_we_n => ddram_we_n,
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ddram_cs_n => open,
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ddram_dm => ddram_dm,
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ddram_dq => ddram_dq,
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ddram_dqs_p => ddram_dqs_p,
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ddram_dqs_n => ddram_dqs_n,
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ddram_clk_p => ddram_clk_p,
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ddram_clk_n => ddram_clk_n,
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ddram_cke => ddram_cke,
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ddram_odt => ddram_odt,
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ddram_reset_n => ddram_reset_n
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);
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led0 <= dram_init_done and not dram_init_error;
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led1 <= dram_init_error; -- Make it blink ?
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soc_rst <= soc_rst_0 or soc_rst_1;
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end generate;
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end architecture behaviour;
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Binary file not shown.
Binary file not shown.
@ -0,0 +1,53 @@
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#ifndef __IO_H
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#define __IO_H
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static inline uint8_t readb(unsigned long addr)
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{
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uint8_t val;
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__asm__ volatile("sync; lbzcix %0,0,%1" : "=r" (val) : "r" (addr) : "memory");
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return val;
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}
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static inline uint16_t readw(unsigned long addr)
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{
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uint16_t val;
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__asm__ volatile("sync; lhzcix %0,0,%1" : "=r" (val) : "r" (addr) : "memory");
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return val;
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}
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|
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static inline uint32_t readl(unsigned long addr)
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{
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uint32_t val;
|
||||
__asm__ volatile("sync; lwzcix %0,0,%1" : "=r" (val) : "r" (addr) : "memory");
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline uint64_t readq(unsigned long addr)
|
||||
{
|
||||
uint64_t val;
|
||||
__asm__ volatile("sync; ldcix %0,0,%1" : "=r" (val) : "r" (addr) : "memory");
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline void writeb(uint8_t val, unsigned long addr)
|
||||
{
|
||||
__asm__ volatile("sync; stbcix %0,0,%1" : : "r" (val), "r" (addr) : "memory");
|
||||
}
|
||||
|
||||
static inline void writew(uint16_t val, unsigned long addr)
|
||||
{
|
||||
__asm__ volatile("sync; sthcix %0,0,%1" : : "r" (val), "r" (addr) : "memory");
|
||||
}
|
||||
|
||||
static inline void writel(uint32_t val, unsigned long addr)
|
||||
{
|
||||
__asm__ volatile("sync; stwcix %0,0,%1" : : "r" (val), "r" (addr) : "memory");
|
||||
}
|
||||
|
||||
static inline void writeq(uint64_t val, unsigned long addr)
|
||||
{
|
||||
__asm__ volatile("sync; stdcix %0,0,%1" : : "r" (val), "r" (addr) : "memory");
|
||||
}
|
||||
|
||||
#endif /* __IO_H */
|
||||
|
||||
@ -0,0 +1,34 @@
|
||||
#ifndef __MICROWATT_SOC_H
|
||||
#define __MICROWATT_SOC_H
|
||||
|
||||
/*
|
||||
* Definitions for the syscon registers
|
||||
*/
|
||||
#define SYSCON_BASE 0xc0000000
|
||||
|
||||
#define SYS_REG_SIGNATURE 0x00
|
||||
#define SYS_REG_INFO 0x08
|
||||
#define SYS_REG_INFO_HAS_UART (1ull << 0)
|
||||
#define SYS_REG_INFO_HAS_DRAM (1ull << 1)
|
||||
#define SYS_REG_BRAMINFO 0x10
|
||||
#define SYS_REG_DRAMINFO 0x18
|
||||
#define SYS_REG_CLKINFO 0x20
|
||||
#define SYS_REG_CTRL 0x28
|
||||
#define SYS_REG_CTRL_DRAM_AT_0 (1ull << 0)
|
||||
#define SYS_REG_CTRL_CORE_RESET (1ull << 1)
|
||||
#define SYS_REG_CTRL_SOC_RESET (1ull << 2)
|
||||
|
||||
/* Definition for the "Potato" UART */
|
||||
#define UART_BASE 0xc0002000
|
||||
|
||||
#define POTATO_CONSOLE_TX 0x00
|
||||
#define POTATO_CONSOLE_RX 0x08
|
||||
#define POTATO_CONSOLE_STATUS 0x10
|
||||
#define POTATO_CONSOLE_STATUS_RX_EMPTY 0x01
|
||||
#define POTATO_CONSOLE_STATUS_TX_EMPTY 0x02
|
||||
#define POTATO_CONSOLE_STATUS_RX_FULL 0x04
|
||||
#define POTATO_CONSOLE_STATUS_TX_FULL 0x08
|
||||
#define POTATO_CONSOLE_CLOCK_DIV 0x18
|
||||
#define POTATO_CONSOLE_IRQ_EN 0x20
|
||||
|
||||
#endif /* __MICROWATT_SOC_H */
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,45 @@
|
||||
#!/usr/bin/python3
|
||||
from fusesoc.capi2.generator import Generator
|
||||
import os
|
||||
import sys
|
||||
import pathlib
|
||||
|
||||
class LiteDRAMGenerator(Generator):
|
||||
def run(self):
|
||||
board = self.config.get('board')
|
||||
|
||||
# Collect a bunch of directory path
|
||||
script_dir = os.path.dirname(sys.argv[0])
|
||||
base_dir = os.path.join(script_dir, os.pardir)
|
||||
gen_dir = os.path.join(base_dir, "generated", board)
|
||||
extras_dir = os.path.join(base_dir, "extras")
|
||||
|
||||
print("Adding LiteDRAM for board... ", board)
|
||||
|
||||
# Grab init-cpu.txt if it exists
|
||||
cpu_file = os.path.join(gen_dir, "init-cpu.txt")
|
||||
if os.path.exists(cpu_file):
|
||||
cpu = pathlib.Path(cpu_file).read_text()
|
||||
else:
|
||||
cpu = None
|
||||
|
||||
# Add files to fusesoc
|
||||
files = []
|
||||
f = os.path.join(gen_dir, "litedram_core.v")
|
||||
files.append({f : {'file_type' : 'verilogSource'}})
|
||||
f = os.path.join(gen_dir, "litedram-wrapper.vhdl")
|
||||
files.append({f : {'file_type' : 'vhdlSource-2008'}})
|
||||
f = os.path.join(gen_dir, "litedram_core.init")
|
||||
files.append({f : {'file_type' : 'user'}})
|
||||
|
||||
# Look for init CPU types and add corresponding files
|
||||
if cpu == "vexriscv":
|
||||
f = os.path.join(base_dir, "extras", "VexRiscv.v")
|
||||
files.append({f : {'file_type' : 'verilogSource'}})
|
||||
|
||||
self.add_files(files)
|
||||
|
||||
g = LiteDRAMGenerator()
|
||||
g.run()
|
||||
g.write()
|
||||
|
||||
@ -0,0 +1,43 @@
|
||||
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
# License: BSD
|
||||
|
||||
{
|
||||
# General ------------------------------------------------------------------
|
||||
"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
|
||||
"cpu_variant":"minimal",
|
||||
"speedgrade": -1, # FPGA speedgrade
|
||||
"memtype": "DDR3", # DRAM type
|
||||
|
||||
# PHY ----------------------------------------------------------------------
|
||||
"cmd_delay": 0, # Command additional delay (in taps)
|
||||
"cmd_latency": 0, # Command additional latency
|
||||
"sdram_module": "MT41K128M16", # SDRAM modules of the board or SO-DIMM
|
||||
"sdram_module_nb": 2, # Number of byte groups
|
||||
"sdram_rank_nb": 1, # Number of ranks
|
||||
"sdram_phy": "A7DDRPHY", # Type of FPGA PHY
|
||||
|
||||
# Electrical ---------------------------------------------------------------
|
||||
"rtt_nom": "60ohm", # Nominal termination
|
||||
"rtt_wr": "60ohm", # Write termination
|
||||
"ron": "34ohm", # Output driver impedance
|
||||
|
||||
# Frequency ----------------------------------------------------------------
|
||||
"input_clk_freq": 100e6, # Input clock frequency
|
||||
"sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk)
|
||||
"iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency
|
||||
|
||||
# Core ---------------------------------------------------------------------
|
||||
"cmd_buffer_depth": 16, # Depth of the command buffer
|
||||
|
||||
# User Ports ---------------------------------------------------------------
|
||||
"user_ports": {
|
||||
"native_0": {
|
||||
"type": "native",
|
||||
},
|
||||
},
|
||||
|
||||
# CSR Port -----------------------------------------------------------------
|
||||
"csr_expose": "False", # expose access to CSR (I/O) ports
|
||||
"csr_align" : 32, # CSR alignment
|
||||
"csr_base" : 0xc0100000 # For cpu=None only
|
||||
}
|
||||
@ -0,0 +1,157 @@
|
||||
#!/usr/bin/python3
|
||||
|
||||
from fusesoc.capi2.generator import Generator
|
||||
from litex.build.tools import write_to_file
|
||||
from litex.build.tools import replace_in_file
|
||||
from litex.build.generic_platform import *
|
||||
from litex.build.xilinx import XilinxPlatform
|
||||
from litex.build.lattice import LatticePlatform
|
||||
from litex.soc.integration.builder import *
|
||||
from litedram.gen import *
|
||||
import subprocess
|
||||
import os
|
||||
import sys
|
||||
import yaml
|
||||
import shutil
|
||||