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caravel-mpw7-20221125
caravel-mpw7-20220822
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trace-test
gitignore
litedram-update
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fix-sdcard
fpu-init
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caravel-mpw6-20220530
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
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dcache-nc-fix
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3 Commits (caravel-mpw7-20220822)

Author SHA1 Message Date
Anton Blanchard 2663326f2c ASIC: Register file updates 
The register file is down from 96 entries to 64, and reads
are synchronous.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 795d57249f ASIC: Reduce multiplier from 4 to 2 cycles 
Our sky130 gate level multiply/adder now makes timing with a single
register stage.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 52f2462232 Add arrays for ASIC flow 
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago