cores
/
microwatt
mirror of https://github.com/antonblanchard/microwatt
3
1
Fork 1
Code Issues Projects Releases Wiki Activity
1,213 Commits
39 Branches
0 Tags
68 MiB
master
caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'caravel-mpw7-20220822'
${ noResults }
Commit Graph

4 Commits (caravel-mpw7-20220822)

Author SHA1 Message Date
Anton Blanchard 64997811a8 Fix power plumbing in execute unit 3 years ago
Anton Blanchard 68495c9b4b ASIC: Switch to ghdl --synth 
Use ghdl --synth to convert to verilog directly instead of going
through Yosys.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 82c8f48f77 ASIC: Fix multiplier power 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 2b47de30c4 Add a script to post process the Microwatt verilog for caravel 
To produce verilog suitable for caravel:

make DOCKER=1 FPGA_TARGET=caravel microwatt_asic.v
./caravel/process-microwatt-verilog.sh

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago