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caravel-mpw7-20221125
caravel-mpw7-20220822
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3 Commits (caravel-mpw7-20221125)

Author SHA1 Message Date
Anton Blanchard 4fc321cd41 Move register stage back after the RAM 
The 512x64 DFFRAM has quite big hold violations that we can hopefully
work around by removing the register stage before the RAM.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2 years ago
Anton Blanchard 01f8ad55ef Move register stage from after RAM to before RAM 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2 years ago
Anton Blanchard 52f2462232 Add arrays for ASIC flow 
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2 years ago