Currently the test writes to the XICS and then checks that the
expected interrupt has happened. This turns into a stbcix
instruction followed immediately by a load from the variable that
indicates whether an interrupt has happened. It is possible for
it to take a few cycles for the store to reach the XICS and the
interrupt request signal to come back to the core, particularly
with improvements to the load/store unit and dcache.
This therefore adds a delay between storing to the XICS and
checking for the occurrence of an interrupt, so as to give the
signals time to propagate. The delay loop does an arbitrary 10
iterations, and each iteration does two loads and one store to
(cacheable) memory.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This changes the SoC interconnect such that the main 64-bit wishbone out
of the processor is first split between only 3 slaves (BRAM, DRAM and a
general "IO" bus) instead of all the slaves in the SoC.
The IO bus leg is then latched and down-converted to 32 bits data width,
before going through a second address decoder for the various IO devices.
This significantly reduces routing and timing pressure on the main bus,
allowing to get rid of frequent timing violations when synthetizing on
small'ish FPGAs such as the Artix-7 35T found on the original Arty board.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
It makes things a bit more standard and a bit nicer to read
without all those strlen(). Also console.c takes care of adding
the carriage returns before the linefeeds.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Checks interrupt masking and priorities.
Adds to `make test_xics` which is run in `make check` also.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Paul Mackerras
Benjamin Herrenschmidt
Michael Neuling