Right now we continually print all 3 possible GPRs an instruction
may be using. Add signals so we only print GPRs when they are
actually read. This should hopefully optimise away when synthesized.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Handle the CR as a single field with per nibble enables. Forward any
writes in the same cycle.
If this proves to be an issue for timing, we may want to revisit
this in the future. For now, it keeps things simple.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This adds support for the Digilane Cmod A7-35.
I had to use the MMCM because the clock (12 MHz) is below the PLL
minimum of 19 MHz.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
I wasn't waiting to get a wishbone ack back on stores before continuing.
This creates all sorts of problems when we add pipelining and send
loads and stores down the pipe faster.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
The old reset code was overly complicated and never worked properly.
Replace it with a simpler sequence that uses a couple of shift registers
to assert resets:
- Wait a number of external clock cycles before removing reset from
the PLL.
- After the PLL locks and the external reset button isn't pressed,
wait a number of PLL clock cycles before removing reset from the SOC.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
The decode2 stage was spaghetti code and needed cleaning up.
Create a series of functions to pull fields from a ppc instruction
and also a series of helpers to extract values for the execution
units.
As suggested by Paul, we should pass all signals to the execution
units and only set the valid signal conditionally, which should
use less resources.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Some VHDL compilers like verific [1] don't like these, so let's remove
them. Lots of random code changes, but passes make check.
Also add basic script to run verific and generate verilog.
1. https://www.verific.com/
Signed-off-by: Michael Neuling <mikey@neuling.org>
- Switch to using ghdl/vunit:llvm, it's a smaller container
- We need to "apt update" before installing packages
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Mikey points out that our stack grows down from 512kB and our
heap is below that too, so we can reduce our BRAM requirements,
which allowing some smaller FPGA boards to work. Not sure why
I thought we were using memory between 512kB and 1MB.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
The synth target can be used to analyze the core after synthesis
without running P&R. Currently, the only edalize backends that
support synthesis without P&R are vivado and icestorm, and icestorm
needs yosys built with verific support to parse vhdl.
To run synthesis only for a part, run
fusesoc run --target=synth --tool=vivado microwatt --part=<part>
where part is a valid Xilinx part such as xc7a100tcsg324-1
Anton Blanchard
Michael Neuling