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caravel-mpw7-20221125
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trace-test
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litedram-update
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2 Commits (0745cca670fd9670022a2c406036032b1129eb1d)

Author SHA1 Message Date
Anton Blanchard 01f8ad55ef Move register stage from after RAM to before RAM 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 52f2462232 Add arrays for ASIC flow 
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago