5 Commits (08c0c4c1b41b3e7d18b9c3fa4a9bdfa42b5f491c)

Author	SHA1	Message	Date
Lars Asplund	08c0c4c1b4	Make core testbenches recognized by VUnit ... This commit also removes the dependencies these testbenches have on VHPIDIRECT. The use of VHPIDIRECT limits the number of available simulators for the project. Rather than using foreign functions the testbenches can be implemented entirely in VHDL where equivalent functionality exists. For these testbenches the VHPIDIRECT-based randomization functions were replaced with VHDL-based functions. The testbenches recognized by VUnit can be executed in parallel threads for better simulation performance using the -p option to the run.py script Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com>	3 years ago
Anton Blanchard	21f482f967	Reformat testbenches ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	3 years ago
Anton Blanchard	ab86b58d95	Exit cleanly from testbench on success ... Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	4 years ago
Paul Mackerras	e08ca4ab8e	countzero: Add a register to help make timing ... This adds a register in the middle of the countzero computation, so that we now have two cycles to count leading or trailing zeroes instead of just one. Execute1 now outputs a one-cycle stall signal when it encounters a cntlz* or cnttz* instruction. With this, the countzero path no longer fails timing on the Artix-7 at 100MHz. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	4 years ago
Paul Mackerras	4396eddc31	countzero: Add a testbench ... Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	5 years ago