cores
/
microwatt
mirror of https://github.com/antonblanchard/microwatt
3
1
Fork 1
Code Issues Projects Releases Wiki Activity
1,001 Commits
39 Branches
0 Tags
66 MiB
master
caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '09bd01a49e'
${ noResults }
Commit Graph

4 Commits (09bd01a49e15e9de1382c666ef794e48df5d3ea7)

Author SHA1 Message Date
Anton Blanchard 34e10cc52c liteeth: Regenerate from upstream litex 
Unfortunately the CSR layout has shifted on upstream litex, so this
is built with the following litex patch backed out:

aad56a047a33 ("integration/soc: Use CSR automatic allocation.")

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 12efb51bcc liteeth: Update yaml config 
csr_data_width is no longer required. Add ntxslots and nrxslots
parameters but set them to the default value.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Anton Blanchard 458dfe01a6 Add liteeth support to Nexys Video 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Benjamin Herrenschmidt 8366710217 liteeth: Hook up LiteX LiteEth ethernet controller 
Currently only generated for Arty.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 4 years ago