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3 Commits (09c8b0332eb46ff7798d422e27b7d2eaac16cca5)

Author SHA1 Message Date
Anton Blanchard 18503732d7 Add ASIC target 3 years ago
Anton Blanchard 5ac715d932 Fix multiplier behavioural 3 years ago
Anton Blanchard 537a0aac1d Add arrays for ASIC flow 
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago