Commit Graph

3 Commits (2843c99a71ad4b88d8d722bb7bae7d4979b6083c)

Author SHA1 Message Date
Michael Neuling e5a30a1358 Wire up sim uart TX interrupt
TX is always ready, so just always sent interrupt when enabled.

No RX interrupt.

Signed-off-by: Michael Neuling <mikey@neuling.org>
4 years ago
Benjamin Herrenschmidt 3ac1dbc737 Share soc.vhdl between FPGA and sim
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt 48b689b665 Add simulated UART design
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago