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caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
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litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
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unused-sig
divider-init
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fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
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1 Commits (290b05f97da6255734b4ff3c7c7a913cf99301f9)

Author SHA1 Message Date
Michael Neuling aae45583d7 Add uart16550 files from fusesoc 
These are needed for synthesis that doesn't use fusesoc natively.

These were pulled in via 'fusesoc fetch ::uart16550:1.5.5-r1'

Signed-off-by: Michael Neuling <mikey@neuling.org>
 4 years ago