Commit Graph

19 Commits (5a3cdc8b226393e1c2b77d44f9b5251a77b77a07)

Author SHA1 Message Date
Paul Mackerras 21ed730514 arty_a7: Add litesdcard interface
This adds litesdcard.v generated from the litex/litesdcard project,
along with logic in top-arty.vhdl to connect it into the system.
There is now a DMA wishbone coming in to soc.vhdl which is narrower
than the other wishbone masters (it has 32-bit data rather than
64-bit) so there is a widening/narrowing adapter between it and the
main wishbone master arbiter.

Also, litesdcard generates a non-pipelined wishbone for its DMA
connection, which needs to be converted to a pipelined wishbone.  We
have a latch on both the incoming and outgoing sides of the wishbone
in order to help make timing (at the cost of two extra cycles of
latency).

litesdcard generates an interrupt signal which is wired up to input 3
of the ICS (IRQ 19).

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
4 years ago
Benjamin Herrenschmidt b230677e93 syscon: Add flag to indicate the timebase frequency
This adds a flag (currently not set) to indicate that the core is using
the architected timebase frequency of 512Mhz. When not set, the core is
using the proc frequency for the timebase.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt d654667304 console: Add support for the 16550 UART
And rebuild various binaries

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt e3941109af console: Cleanup console API
Use a more generic console_init() instead of potato_uart_init(),
and do the same for interrupt control. There should be no
change in behaviour.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 7575b1e0c2 uart: Import and hook up opencore 16550 compatible UART
This imports via fusesoc a 16550 compatible (ie "standard") UART,
and wires it up optionally in the SoC instead of the potato one.

This also adds support for a second UART (which is always a
16550) to Arty, wired to JC "bottom" port.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 8366710217 liteeth: Hook up LiteX LiteEth ethernet controller
Currently only generated for Arty.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 5c2fc47e2c xics: Add simple ICS
Move the external interrupt generation to a separate module
"ICS" (source controller) which a register per source containing
currently only the priority control.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt 67b6117ebf soc: Slight cleanup of IRQ assignments
Use a separate process to assign selected interrupts to the
interrupt array, and document them.

There's only one interrupt *for now* but that will change
and this way is clearer.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt f9f18906a3 soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding
This makes the control bus currently going out of "soc" towards
litedram more generic for external IO devices added by the
top-level rather than inside the SoC proper.

This is mostly renaming of signals and a small change on how the
address decoder operates, using a separate "cascaded" decode for
the external IOs.

We make the region 0xc8nn_nnnn be the "external IO" region for
now.

This will make it easier / cleaner to add more external devices.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt 6aadad5a75 spi: Add booting from flash to litedram init
It will look for an ELF binary at the flash offset specified
for the board (currently 0x300000 on Arty but that could be
changed).

Note: litedram is regenerated in order to rebuild the init code,
which was done using a newer version of litedram from LiteX.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt cc4dcb3597 spi: Add SPI Flash controller
This adds an SPI flash controller which supports direct
memory-mapped access to the flash along with a manual
mode to send commands.

The direct mode can be set via generic to default to single
wire or quad mode. The controller supports normal, dual and quad
accesses with configurable commands, clock divider, dummy clocks
etc...

The SPI clock can be an even divider of sys_clk starting at 2
(so max 50Mhz with our typical Arty designs).

A flash offset is carried via generics to syscon to tell SW about
which portion of the flash is reserved for the FPGA bitfile. There
is currently no plumbing to make the CPU reset past that address (TBD).

Note: Operating at 50Mhz has proven unreliable without adding some
delay to the sampling of the input data. I'm working in improving
this, in the meantime, I'm leaving the default set at 25 Mhz.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt 3167515069 sw: Properly mask syscon register fields
Some fields might get extended with extra bits, use the appropriate
masks when reading the values.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt bf1b98b958 litedram: Add support for booting without BRAM
This adds an option to disable the main BRAM and instead copy a
payload stashed along with the init code in the secondary BRAM
into DRAM and boot from there

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt 573b6b4bc4 soc: Rework interconnect
This changes the SoC interconnect such that the main 64-bit wishbone out
of the processor is first split between only 3 slaves (BRAM, DRAM and a
general "IO" bus) instead of all the slaves in the SoC.

The IO bus leg is then latched and down-converted to 32 bits data width,
before going through a second address decoder for the various IO devices.

This significantly reduces routing and timing pressure on the main bus,
allowing to get rid of frequent timing violations when synthetizing on
small'ish FPGAs such as the Artix-7 35T found on the original Arty board.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt 8d64090a68 sw: Add full memory map to .h and use it for litedram .lds
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt c19b5b8cc7 litedram: Update to new LiteX/LiteDRAM version
Things have changed a bit in upstream LiteX. LiteDRAM now exposes a
wishbone for the CSRs for example.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt edbbf9a125 console: Remove putstr()
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt 7bc118c7db console: Move console files
console.c goes to a new lib/ where we'll store other general utilities
and console.h goes to include/

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago
Benjamin Herrenschmidt 33de131384 Add microwatt_soc.h and io.h include file
This contains C definitions for various Microwatt internal MMIOs
and a set of accessors.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago