Commit Graph

4 Commits (5ee86e7621966f4b1496d10837ae660749a64ac8)

Author SHA1 Message Date
Michael Neuling 4d5abfb430 Remove dynamic ranges from code
Some VHDL compilers like verific [1] don't like these, so let's remove
them. Lots of random code changes, but passes make check.

Also add basic script to run verific and generate verilog.

1. https://www.verific.com/

Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years ago
Anton Blanchard 0fd18c2455 Add srd and srw
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard 73daacbcd4 Add sim only divw
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years ago