795d57249f
ASIC: Reduce multiplier from 4 to 2 cycles
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Our sky130 gate level multiply/adder now makes timing with a single
register stage.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
Anton Blanchard
4fc321cd41
Move register stage back after the RAM
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The 512x64 DFFRAM has quite big hold violations that we can hopefully
work around by removing the register stage before the RAM.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
Anton Blanchard
d2cc31cde4
Add simplebus
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
Anton Blanchard
6745d9dd5f
Hook up JTAG to ASIC top level
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
28debecf1a
Add ASIC target
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
Anton Blanchard
01f8ad55ef
Move register stage from after RAM to before RAM
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
52f2462232
Add arrays for ASIC flow
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Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
Anton Blanchard
Anton Blanchard