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caravel-mpw7-20221125
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trace-test
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litedram-update
liteeth-update
fix-sdcard
fpu-init
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fpu-typo
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caravel-mpw6-20220530
caravel-mpw5-20220323
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
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orange-crab-freq
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remove-potato-uart
cache-tlb-parameters-2
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3 Commits (6baf3b519f5d304b3d464114454e6f57e3216fea)

Author SHA1 Message Date
Benjamin Herrenschmidt bf1b98b958 litedram: Add support for booting without BRAM 
This adds an option to disable the main BRAM and instead copy a
payload stashed along with the init code in the secondary BRAM
into DRAM and boot from there

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Anton Blanchard 488c30fe91 Add log2ceil and use it in bram code 
We might want a non power of 2 amount of RAM in order to fit into an
FPGA, so create log2ceil and use it when calculating the number of
memory bits.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Benjamin Herrenschmidt 9a63c098a5 Move log2/ispow2 to a utils package 
(Out of icache and dcache)


Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago