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2 Commits (6dbc7c0559d0d109c0c91985180d57a6e7eedb88)

Author SHA1 Message Date
Anton Blanchard 17d533219b First pass at an external JTAG port 
The verilator simulation interface uses the remote_bitbang
protocol from openocd. I have a simple implementation for
urjtag too.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 3e8a6a8fc2 Add yosys/verilator support 
Add a microwatt-verilator target that simulates the
ghdl -> yosys -> verilog -> verilator path. A good test of
ghdl/yosys synthesis.

Because the everything is run through synthesis, the instruction
image is baked into the build via the RAM_INIT_FILE generic.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago