Commit Graph

9 Commits (780d6c754c8535de862b1e50dc23e1367116ef39)

Author SHA1 Message Date
Anton Blanchard 780d6c754c litedram: Regenerate from upstream litex
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago
Benjamin Herrenschmidt ac81bb17ac litedram: Regenerate
This regenerate litedram for all targets (genesys2 is new in this
build) using the latest LiteX.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 6aadad5a75 spi: Add booting from flash to litedram init
It will look for an ELF binary at the flash offset specified
for the board (currently 0x300000 on Arty but that could be
changed).

Note: litedram is regenerated in order to rebuild the init code,
which was done using a newer version of litedram from LiteX.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 599fad117b litedram: Remove old "VexRiscV" based initializations
Support for this has bitrotted and would require refactoring of L2 to
be brought back. It's also not really needed anymore now that we ship
pre-generated litedram and that LiteX supports what we do.

So take it out, which simplifies some of the scripts as well. This also
fixes up CSR alignment the sim model.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt eaf6883e57 litedram: Update to latest LiteX/LiteDRAM version
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 6828e93113 litedram: Test bench
The test bench test simple access forms for now, it's a starting point
but it already helped find/fix a bug.

Includes a litedram update to be able to operate the sim model without
inits.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt a3857aac94 litedram: Add an L2 cache with store queue
This adds a cache between the wishbone and litedram with the following
features (at this point, it's still evolving)

  - 128 bytes line width in order to have a reasonable amount of
litedram pipelining on the 128-bit wide data port.

  - Configurable geometry otherwise

  - Stores are acked immediately on wishbone whether hit or miss
(minus a 2 cycles delay if there's a previous load response in the
way) and sent to LiteDRAM via 8 entries (configurable) store queue

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt bf1b98b958 litedram: Add support for booting without BRAM
This adds an option to disable the main BRAM and instead copy a
payload stashed along with the init code in the secondary BRAM
into DRAM and boot from there

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago
Benjamin Herrenschmidt 6fe077910b litedram: Add simulation support
This adds a simulated litedram model along with the necessary
Makefile gunk to verilate it and wrap it for use by ghdl.

The core_dram_tb test bench is a variant of core_tb with
LiteDRAM simulated. It's not built by default, an explicit

make core_dram_tb

is necessary as to not require verilator to be installed for
the normal build process (also it's slow'ish).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 years ago