An extra uart is added at 0xc0008000 attached to valentyusb, using
the OrangeCrab's onboard USB port.
This has a liteuart interface, an identifier bit is added to syscon.
Generated from branch hw_cdc_eptri of
https://github.com/litex-hub/valentyusb
The generate script is based on valentyusb/sim/generate_verilog.py
UARTUSB: usbserial@8000 {
device_type = "serial";
compatible = "litex,liteuart";
reg = <0x8000 0x100>;
interrupts = <0x15 0x1>;
};
(requires extra kernel patches for early console at present v5.16)
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
Matt Johnston