Commit Graph

1 Commits (9366d23f1fb6b03456bb857a3a52bfaada095580)

Author SHA1 Message Date
Anton Blanchard 52f2462232 Add arrays for ASIC flow
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2 years ago