cores
/
microwatt
mirror of https://github.com/antonblanchard/microwatt
3
1
Fork 1
Code Issues Projects Releases Wiki Activity
74 Commits
39 Branches
0 Tags
66 MiB
master
caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '9687034d78'
${ noResults }
Commit Graph

3 Commits (9687034d784b83b3dc3944143e1edb2a10ffc1b6)

Author SHA1 Message Date
Benjamin Herrenschmidt 8bfd6e5eae Use simulated UART in core test bench 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Anton Blanchard 1fa0b332ca micropython only requires 512kB of BRAM 
Mikey points out that our stack grows down from 512kB and our
heap is below that too, so we can reduce our BRAM requirements,
which allowing some smaller FPGA boards to work. Not sure why
I thought we were using memory between 512kB and 1MB.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 5a29cb4699 Initial import of microwatt 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago