cores
/
microwatt
mirror of https://github.com/antonblanchard/microwatt
3
1
Fork 1
Code Issues Projects Releases Wiki Activity
1,133 Commits
39 Branches
0 Tags
67 MiB
master
caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
gitignore
litedram-update
liteeth-update
fix-sdcard
fpu-init
loadstore-init
core_debug-init
icache-unused-sig
icache-insn-u-state
dcache-unused-sig
unused-sig
divider-init
loadstore-pmu-init
icache-pmu-events
fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
jtag-port
nia-debug
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '9a8a8e50f8'
${ noResults }
Commit Graph

2 Commits (9a8a8e50f8e886a90315091fe8d9e584c8429493)

Author SHA1 Message Date
Paul Mackerras ec5730a75a tests: Add tests for lq/stq and lqarx/stqcx. 
Lq and stq are tested in both BE and LE modes (though only 64-bit
mode) by the 'modes' test.

Lqarx and stqcx. are tested by the 'reservation' test in LE mode mode
(64-bit).

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 5 years ago
Paul Mackerras e7a08f33eb tests: Add a test for the load-reserve and store-conditional instructions 
This checks that the instructions seem to update memory as expected,
and also that they generate alignment interrupts when necessary.
We don't check whether the memory update is atomic as we don't have
SMP yet.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 5 years ago