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caravel-mpw7-20221125
caravel-mpw7-20220822
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trace-test
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litedram-update
liteeth-update
fix-sdcard
fpu-init
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core_debug-init
icache-unused-sig
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divider-init
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fpu-typo
less-fpga-init
caravel-mpw6-20220530
caravel-mpw5-20220323
caravel-mpw5-20220322
alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
icbi-issue
orange-crab-freq
dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
caravel-20210105
jtag-port-2
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nia-debug
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1 Commits (9ccf9a7f8000e652557729e5b2903f86e91eb7a5)

Author SHA1 Message Date
Anton Blanchard 185bcba6bb Add a simple test case 
We use 2 32bit RAMs, so we need to split the test case into
two files.
 4 years ago