microwatt

Commit Graph

Author	SHA1	Message	Date
Anton Blanchard	8acd5a5607	verilator: Specify top level module While verilator finds the correct top level module with the current setup, if we start adding simulation models it can get confused. Explicitly specify the top level module. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	5 years ago
Anton Blanchard	3e8a6a8fc2	Add yosys/verilator support Add a microwatt-verilator target that simulates the ghdl -> yosys -> verilog -> verilator path. A good test of ghdl/yosys synthesis. Because the everything is run through synthesis, the instruction image is baked into the build via the RAM_INIT_FILE generic. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>	6 years ago

Author

SHA1

Message

Date

Anton Blanchard

8acd5a5607

verilator: Specify top level module

While verilator finds the correct top level module with the current
setup, if we start adding simulation models it can get confused.

Explicitly specify the top level module.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

Anton Blanchard

3e8a6a8fc2

Add yosys/verilator support

Add a microwatt-verilator target that simulates the
ghdl -> yosys -> verilog -> verilator path. A good test of
ghdl/yosys synthesis.

Because the everything is run through synthesis, the instruction
image is baked into the build via the RAM_INIT_FILE generic.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

2 Commits (a1d83ba91a17e2812e8f3d99e01df9ca05deb414)