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caravel-mpw7-20221125
caravel-mpw7-20220822
branch-alias
trace-test
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litedram-update
liteeth-update
fix-sdcard
fpu-init
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core_debug-init
icache-unused-sig
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caravel-mpw6-20220530
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
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dcache-nc-fix
remove-potato-uart
cache-tlb-parameters-2
caravel-20210114
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2 Commits (b8f9c833f85a13514f61b64895fa9ae6f7c2d671)

Author SHA1 Message Date
Anton Blanchard 83fe8b629c litesdcard: Fix and regenerate Verilog 
Fix the litex generate script to pass frequencies in Hz. Regenerate
the litesdcard Verilog for both Xilinx and Lattice. This fixes
litesdcard on my Nexys Video.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 3 years ago
Matt Johnston 42959184dd litesdcard: add lattice, regenerate 
Modifies litescard generate script to take a clock speed.

Regenerated verilog with latest litesdcard
e52c731 ("Bump year.")

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
 3 years ago