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microwatt
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caravel-mpw7-20221125
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litedram-update
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1 Commits (c164a2f4eaa5cce2494d3716b2a81e51178ccda7)

Author SHA1 Message Date
Benjamin Herrenschmidt 025cf5efe8 syscon: Add syscon registers 
These provides some info about the SoC (though it's still somewhat
incomplete and needs more work, see comments).

There's also a control register for selecting DRAM vs. BRAM at 0
(and for soft-resetting the SoC but that isn't wired up yet).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 4 years ago