microwatt

Commit Graph

Author	SHA1	Message	Date
Benjamin Herrenschmidt	39c2abae51	Fix build of core_dram_tb and dram_tb and fix tracing We disabled --trace by default, so we need to stop linking verilated_vcd_c.o as it doesn't exist in that case. While at it, make a Makefile variable to enable/disable verilator tracing and add a couple of generics to those test benches to control tracing in the L2 and in litedram. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	3 years ago
Benjamin Herrenschmidt	6fe077910b	litedram: Add simulation support This adds a simulated litedram model along with the necessary Makefile gunk to verilate it and wrap it for use by ghdl. The core_dram_tb test bench is a variant of core_tb with LiteDRAM simulated. It's not built by default, an explicit make core_dram_tb is necessary as to not require verilator to be installed for the normal build process (also it's slow'ish). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago

Author

SHA1

Message

Date

Benjamin Herrenschmidt

39c2abae51

Fix build of core_dram_tb and dram_tb and fix tracing

We disabled --trace by default, so we need to stop linking verilated_vcd_c.o
as it doesn't exist in that case.

While at it, make a Makefile variable to enable/disable verilator tracing
and add a couple of generics to those test benches to control tracing
in the L2 and in litedram.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Benjamin Herrenschmidt

6fe077910b

litedram: Add simulation support

This adds a simulated litedram model along with the necessary
Makefile gunk to verilate it and wrap it for use by ghdl.

The core_dram_tb test bench is a variant of core_tb with
LiteDRAM simulated. It's not built by default, an explicit

make core_dram_tb

is necessary as to not require verilator to be installed for
the normal build process (also it's slow'ish).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

2 Commits (ce5a967ac2cdb7912c20941cc01b587a12a50016)