Commit Graph

1 Commits (d504ae63f6021fdfb2dd07b7dad08086e3772128)

Author SHA1 Message Date
Anton Blanchard 8ecb30da05 Add arrays for ASIC flow
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
3 years ago