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3 Commits (d852dedfe4cb6e98406c38cca9e40c2336c51875)

Author SHA1 Message Date
Anton Blanchard 5e8ba5acb0 First pass at an external JTAG port 
The verilator simulation interface uses the remote_bitbang
protocol from openocd. I have a simple implementation for
urjtag too.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 4 years ago
Anton Blanchard 04c56a0c52 Pass clock frequency to UART sim wrapper 
The UART sim wrapper is currently hard wired to 50 MHz.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago
Anton Blanchard 3e8a6a8fc2 Add yosys/verilator support 
Add a microwatt-verilator target that simulates the
ghdl -> yosys -> verilog -> verilator path. A good test of
ghdl/yosys synthesis.

Because the everything is run through synthesis, the instruction
image is baked into the build via the RAM_INIT_FILE generic.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 5 years ago