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caravel-mpw7-20221125
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trace-test
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litedram-update
liteeth-update
fix-sdcard
fpu-init
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alt-reset-address
log2ceil-issue
fpu-constant
asic-3
boxarty-20211011
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remove-potato-uart
cache-tlb-parameters-2
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jtag-port-2
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5 Commits (e08ca4ab8eba7bec404f82396e41d3b5c616b94d)

Author SHA1 Message Date
Anton Blanchard 20674e0d65 Add SPI configuration to Xilinx constraint files 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard 14da542d4a
Merge pull request #20 from antonblanchard/reset-rework2 
Rework reset code
 6 years ago
Anton Blanchard 63295526ad Add CONFIG_VOLTAGE and CFGBVS entries 
Remove a couple of warnings from Vivado.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Anton Blanchard a53ad60014 Rename a few reset signals 
clk -> ext_clk
reset_n -> ext_rst
reset -> rst

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 6 years ago
Olof Kindgren abca85b034 Add constraint file for Nexys A7 6 years ago