If the generic USE_LCD is false, the first SD card controller (mmcblk0
in Linux) is connected to pmod HA; if USE_LCD is true, it is connected
to the SD card slot on the touchscreen/LCD panel.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This adds connections from the A2 - A5 inputs on the Arty A7 to the
XADC module in the Artix-7 plus a way for software to access the XADC
via its DRP port, and a status register to tell software when
conversion sequences are done.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This adds an interface for an Arduino-compatible LCD touchscreen. The
screen module plugs directly on to the Arduino/chipKit shield
connector on the Arty A7. Unfortunately, the slightly strange way the
resistive touchscreen is brought out (connected to the D0, D1, RS and
CS pins) combined with the 200 ohm protection resisters on the Arty
board mean that some hardware hacks to the module are necessary. I
rewired mine so that D0 and D1 are on the A4 and A5 pins and the reset
is where D0 was (shield I/O 8).
This interface is suitable for boards with a HX8347 driver chip. The
timing may not be quite suitable for other driver chips.
The interface is a byte which can be read and written at 0xc8050000,
containing an index register, and a 1-8 byte data register at
0xc8050008. Reading at offsets 1 to 7 from those addresses yields the
same value as at offset 0. Writing 64 bits to the data register
writes the bytes at offset 1, 0, 3, 2, 5, 4, 7, 6 in that order to the
driver chip. This allows pixel data to be transferred using 64-bit
writes, ending up in the frame buffer in the expected order (for
16-bit pixels, the driver chip expects MS byte then LS byte). 32-bit
writes do 1, 0, 3, 2, and 16-bit writes do 1, 0.
The touchscreen support so far is a 1-byte register containing bits to
set RS, D0, D1 and CS high or low or make them tri-state. There is
nothing to do analog conversions of the signal levels at this stage.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This adds a second SD card interface. The main complexity is in
providing a wishbone switch/arbiter to multiplex the two DMA
wishbones from the two interfaces to a single wishbone going to
the soc module. There is a new syscon info reg bit to indicate the
presence of the second litesdcard.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Currently, GPIO lines 0 - 8 drive three of the 3-colour LEDs on
output, but on input read the state of the pins labelled IO10 - IO13,
IO26 - IO29 and IO8 on the Arty board. Then GPIO lines 10 - 17 drive
IO10 - IO13 and IO26 - IO29 on output, but on input read the 4 buttons
and 4 switches. To simplify all this and prepare for future changes,
this just detaches IO8, IO13 - IO13 and IO26 - IO29, so now GPIO 0 - 8
read 0 on input, and GPIO 10 - 17 do nothing on output.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Commit 0ceace927c ("Xilinx FPGAs: Eliminate Vivado critical
warnings", 2024-03-08) incorrectly removed the constraints for
shield_io36 through to shield_io44 (due to me applying the wrong
version of a patch), resulting in Vivado giving compile errors when
building for the Arty A7. This restores the constraints.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This resolves various warnings and critical warnings from Vivado.
In particular, the asynchronous loops in the xilinx hardware RNG were
giving a lot of critical warnings, which proved to be difficult to
suppress, so this instead makes all the xilinx platforms use the
'nonrandom.vhdl' implementation, which always returns an error.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Make the shield I/O pins be individual signals rather than a bus in
order to avoid warnings on pins which don't have both a driver and a
receiver.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This adds litesdcard.v generated from the litex/litesdcard project,
along with logic in top-arty.vhdl to connect it into the system.
There is now a DMA wishbone coming in to soc.vhdl which is narrower
than the other wishbone masters (it has 32-bit data rather than
64-bit) so there is a widening/narrowing adapter between it and the
main wishbone master arbiter.
Also, litesdcard generates a non-pipelined wishbone for its DMA
connection, which needs to be converted to a pipelined wishbone. We
have a latch on both the incoming and outgoing sides of the wishbone
in order to help make timing (at the cost of two extra cycles of
latency).
litesdcard generates an interrupt signal which is wired up to input 3
of the ICS (IRQ 19).
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This adds a GPIO controller which provides 32 bits of I/O. The
registers are modelled on the set used by the gpio-ftgpio010.c driver
in the Linux kernel. Currently there is no interrupt capability
implemented, though an interrupt line from the GPIO subsystem to the
XICS has been connected.
For the Arty A7 board, GPIO lines 0 to 13 are connected to the pins
labelled IO0 to IO13 on the "shield" connector, GPIO lines 14 to 29
connect to IO26 to IO41, GPIO line 30 connects to the pin labelled A
(aka IO42), and GPIO line 31 is connected to LED 7.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This adds, as comments, lines which would if uncommented define
properties which associate the pins of the headers on the Arty A7
board with FPGA pins. It also adds properties for LEDs 1--3, also
commented out for now.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This imports via fusesoc a 16550 compatible (ie "standard") UART,
and wires it up optionally in the SoC instead of the potato one.
This also adds support for a second UART (which is always a
16550) to Arty, wired to JC "bottom" port.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
No cells matched 'get_cells -hierarchical -filter {NAME =~*/spi_rxtx/dat_i_l*}'. [build/microwatt_0/src/microwatt_0/fpga/arty_a7.xdc:42]
The signal is in it's own process so the net name ends up being
spi_rxtx/input_delay_1.dat_i_l_reg.
After this change the log shows:
Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42).
Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42).
Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42).
Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42).
Signed-off-by: Joel Stanley <joel@jms.id.au>
This adds an SPI flash controller which supports direct
memory-mapped access to the flash along with a manual
mode to send commands.
The direct mode can be set via generic to default to single
wire or quad mode. The controller supports normal, dual and quad
accesses with configurable commands, clock divider, dummy clocks
etc...
The SPI clock can be an even divider of sys_clk starting at 2
(so max 50Mhz with our typical Arty designs).
A flash offset is carried via generics to syscon to tell SW about
which portion of the flash is reserved for the FPGA bitfile. There
is currently no plumbing to make the CPU reset past that address (TBD).
Note: Operating at 50Mhz has proven unreliable without adding some
delay to the sampling of the input data. I'm working in improving
this, in the meantime, I'm leaving the default set at 25 Mhz.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The DRAM related pins have some small changes in LiteX, so resync
and add the false path information as well.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The old toplevel.vhdl becomes top-generic.vhdl, which is to be used
by platforms that do not have a litedram option.
Arty has its own top-arty.vhdl which supports litedram and is now
hooked up
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Paul Mackerras
Matt Johnston
Michael Neuling