cores
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microwatt
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caravel-mpw7-20221125
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litedram-update
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3 Commits (f089f2145a28220075bfefdcf92133a3717922d4)

Author SHA1 Message Date
Michael Neuling e5a30a1358 Wire up sim uart TX interrupt 
TX is always ready, so just always sent interrupt when enabled.

No RX interrupt.

Signed-off-by: Michael Neuling <mikey@neuling.org>
 5 years ago
Benjamin Herrenschmidt 3ac1dbc737 Share soc.vhdl between FPGA and sim 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago
Benjamin Herrenschmidt 48b689b665 Add simulated UART design 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 5 years ago