3 Commits (f9dc3ecdc811dcc8b55ba3915b23c36b9e3d6052)

Author	SHA1	Message	Date
Paul Mackerras	0ceace927c	Xilinx FPGAs: Eliminate Vivado critical warnings ... This resolves various warnings and critical warnings from Vivado. In particular, the asynchronous loops in the xilinx hardware RNG were giving a lot of critical warnings, which proved to be difficult to suppress, so this instead makes all the xilinx platforms use the 'nonrandom.vhdl' implementation, which always returns an error. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	2 years ago
Paul Mackerras	e02d8060ed	Change the multiplier interface to support signed multipliers ... This adds an 'is_signed' signal to MultiplyInputType to indicate whether the data1 and data2 fields are to be interpreted as signed or unsigned numbers. The 'not_result' field is replaced by a 'subtract' field which provides a more intuitive interface for requesting that the product be subtracted from the addend rather than added, i.e. subtract = 1 gives C - A * B, vs. subtract = 0 giving C + A * B. (Previously the users of the multipliers got the same effect by complementing the addend and setting not_result = 1.) The is_32bit field is removed because it is no longer used now that we have a separate 32-bit multiplier. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	3 years ago
Paul Mackerras	595a758400	execute1: Add a pipelined 33-bit signed multiplier ... This adds a pipelined 33-bit by 33-bit signed multiplier with one cycle latency to the execute pipeline, and uses it for the mullw, mulhw and mulhwu instructions. Because it has one cycle of latency we can assume that its result is available in the second execute stage without needing to add busy logic to the second stage. This adds both a generic version of the multiplier and a Xilinx-specific version using four DSP slices of the Artix-7. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	3 years ago