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Raptor Engineering Development Team fcb783a0fb Extend LiteDRAM VHDL wrapper to allow more than one clock line ... This is necessary for the upcoming Arctic Tern system enablement, since Arctic Tern uses two DRAM devices and a separate clock line is routed to each device. LiteX handles this behavior correctly, therefore we assume other hardware exists that uses a similar DRAM clock design. Updates from Mikey to fix some compile issues. Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Michael Neuling <mikey@neuling.org>		4 years ago
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fusesoc-add-files.py	litedram: Remove old "VexRiscV" based initializations	5 years ago
litedram-wrapper-l2.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	4 years ago
sim_dram_verilate.mk	litedram: Add simulation support	5 years ago
sim_litedram.vhdl	Extend LiteDRAM VHDL wrapper to allow more than one clock line	4 years ago
sim_litedram_c.cpp	litedram: Add simulation support	5 years ago
wave.gtkw	litedram: Add an L2 cache with store queue	5 years ago
wave.opt	litedram: Add an L2 cache with store queue	5 years ago
wave_tb.gtkw	litedram: l2: Latency improvements	5 years ago