A tiny Open POWER ISA softcore written in VHDL 2008

openpowerppc64leprocessorvhdl

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Branch: master

alt-reset-address

asic-3

boxarty-20211011

branch-alias

cache-tlb-parameters-2

caravel-20210105

caravel-20210114

caravel-mpw5-20220322

caravel-mpw5-20220323

caravel-mpw6-20220530

caravel-mpw7-20220822

caravel-mpw7-20221125

core_debug-init

dcache-nc-fix

dcache-unused-sig

divider-init

fix-sdcard

fpu-constant

fpu-init

fpu-typo

gitignore

icache-insn-u-state

icache-pmu-events

icache-unused-sig

icbi-issue

jtag-port

jtag-port-2

less-fpga-init

litedram-update

liteeth-update

loadstore-init

loadstore-pmu-init

log2ceil-issue

master

nia-debug

orange-crab-freq

remove-potato-uart

trace-test

unused-sig

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microwatt/constraints

History

Matt Johnston a9b467f43b orangecrab: add Orange Crab r0.2 target ... top-orangecrab0.2 is a copy of top-arty with various changes. USRMCLK is added for the SPI clock ethernet is removed Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>		1 year ago
..
ecp5-evn.lpf	Initial support for ghdl synthesis	3 years ago
orange-crab-0.2.lpf	orangecrab: add Orange Crab r0.2 target	1 year ago
orange-crab.lpf	Initial support for ghdl synthesis	3 years ago