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443 lines
16 KiB
VHDL
443 lines
16 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.utils.all;
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use work.common.all;
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entity fetch1 is
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generic(
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RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0');
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ALT_RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0');
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TLB_SIZE : positive := 64; -- L1 ITLB number of entries (direct mapped)
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HAS_BTC : boolean := true
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);
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port(
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clk : in std_ulogic;
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rst : in std_ulogic;
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-- Control inputs:
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stall_in : in std_ulogic;
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flush_in : in std_ulogic;
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inval_btc : in std_ulogic;
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stop_in : in std_ulogic;
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alt_reset_in : in std_ulogic;
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m_in : in MmuToITLBType;
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-- redirect from writeback unit
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w_in : in WritebackToFetch1Type;
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-- redirect from decode1
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d_in : in Decode1ToFetch1Type;
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-- Request to icache
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i_out : out Fetch1ToIcacheType;
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-- outputs to logger
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log_out : out std_ulogic_vector(42 downto 0)
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);
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end entity fetch1;
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architecture behaviour of fetch1 is
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type reg_internal_t is record
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mode_32bit: std_ulogic;
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rd_is_niap4: std_ulogic;
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tlbcheck: std_ulogic;
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tlbstall: std_ulogic;
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next_nia: std_ulogic_vector(63 downto 0);
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end record;
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-- Mini effective to real translation cache
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type erat_t is record
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epn0: std_ulogic_vector(63 - MIN_LG_PGSZ downto 0);
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epn1: std_ulogic_vector(63 - MIN_LG_PGSZ downto 0);
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rpn0: std_ulogic_vector(REAL_ADDR_BITS - MIN_LG_PGSZ - 1 downto 0);
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rpn1: std_ulogic_vector(REAL_ADDR_BITS - MIN_LG_PGSZ - 1 downto 0);
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priv0: std_ulogic;
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priv1: std_ulogic;
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valid: std_ulogic_vector(1 downto 0);
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mru: std_ulogic; -- '1' => entry 1 most recently used
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end record;
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signal r, r_next : Fetch1ToIcacheType;
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signal r_int, r_next_int : reg_internal_t;
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signal advance_nia : std_ulogic;
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signal log_nia : std_ulogic_vector(42 downto 0);
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signal erat : erat_t;
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signal erat_hit : std_ulogic;
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signal erat_sel : std_ulogic;
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constant BTC_ADDR_BITS : integer := 10;
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constant BTC_TAG_BITS : integer := 62 - BTC_ADDR_BITS;
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constant BTC_TARGET_BITS : integer := 62;
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constant BTC_SIZE : integer := 2 ** BTC_ADDR_BITS;
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constant BTC_WIDTH : integer := BTC_TAG_BITS + BTC_TARGET_BITS + 2;
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type btc_mem_type is array (0 to BTC_SIZE - 1) of std_ulogic_vector(BTC_WIDTH - 1 downto 0);
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signal btc_rd_addr : unsigned(BTC_ADDR_BITS - 1 downto 0);
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signal btc_rd_data : std_ulogic_vector(BTC_WIDTH - 1 downto 0) := (others => '0');
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signal btc_rd_valid : std_ulogic := '0';
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-- L1 ITLB.
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constant TLB_BITS : natural := log2(TLB_SIZE);
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constant TLB_EA_TAG_BITS : natural := 64 - (MIN_LG_PGSZ + TLB_BITS);
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constant TLB_PTE_BITS : natural := 64;
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subtype tlb_index_t is integer range 0 to TLB_SIZE - 1;
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type tlb_valids_t is array(tlb_index_t) of std_ulogic;
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subtype tlb_tag_t is std_ulogic_vector(TLB_EA_TAG_BITS - 1 downto 0);
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type tlb_tags_t is array(tlb_index_t) of tlb_tag_t;
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subtype tlb_pte_t is std_ulogic_vector(TLB_PTE_BITS - 1 downto 0);
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type tlb_ptes_t is array(tlb_index_t) of tlb_pte_t;
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signal itlb_valids : tlb_valids_t;
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signal itlb_tags : tlb_tags_t;
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signal itlb_ptes : tlb_ptes_t;
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-- Values read from above arrays on a clock edge
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signal itlb_valid : std_ulogic;
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signal itlb_ttag : tlb_tag_t;
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signal itlb_pte : tlb_pte_t;
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signal itlb_hit : std_ulogic;
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-- Simple hash for direct-mapped TLB index
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function hash_ea(addr: std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
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variable hash : std_ulogic_vector(TLB_BITS - 1 downto 0);
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begin
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hash := addr(MIN_LG_PGSZ + TLB_BITS - 1 downto MIN_LG_PGSZ)
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xor addr(MIN_LG_PGSZ + 2 * TLB_BITS - 1 downto MIN_LG_PGSZ + TLB_BITS)
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xor addr(MIN_LG_PGSZ + 3 * TLB_BITS - 1 downto MIN_LG_PGSZ + 2 * TLB_BITS);
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return hash;
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end;
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begin
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regs : process(clk)
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begin
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if rising_edge(clk) then
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log_nia <= r.nia(63) & r.nia(43 downto 2);
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if r /= r_next and advance_nia = '1' then
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report "fetch1 rst:" & std_ulogic'image(rst) &
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" IR:" & std_ulogic'image(r_next.virt_mode) &
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" P:" & std_ulogic'image(r_next.priv_mode) &
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" E:" & std_ulogic'image(r_next.big_endian) &
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" 32:" & std_ulogic'image(r_next_int.mode_32bit) &
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" I:" & std_ulogic'image(w_in.interrupt) &
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" R:" & std_ulogic'image(w_in.redirect) & std_ulogic'image(d_in.redirect) &
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" S:" & std_ulogic'image(stall_in) &
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" T:" & std_ulogic'image(stop_in) &
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" nia:" & to_hstring(r_next.nia) &
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" req:" & std_ulogic'image(r_next.req) &
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" FF:" & std_ulogic'image(r_next.fetch_fail);
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end if;
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if advance_nia = '1' then
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r <= r_next;
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r_int <= r_next_int;
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end if;
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-- always send the up-to-date stop mark and req
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r.stop_mark <= stop_in;
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r.req <= r_next.req;
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r.fetch_fail <= r_next.fetch_fail;
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r_int.tlbcheck <= r_next_int.tlbcheck;
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r_int.tlbstall <= r_next_int.tlbstall;
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end if;
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end process;
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log_out <= log_nia;
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btc : if HAS_BTC generate
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signal btc_memory : btc_mem_type;
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attribute ram_style : string;
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attribute ram_style of btc_memory : signal is "block";
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signal btc_valids : std_ulogic_vector(BTC_SIZE - 1 downto 0);
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-- attribute ram_style of btc_valids : signal is "distributed";
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signal btc_wr : std_ulogic;
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signal btc_wr_data : std_ulogic_vector(BTC_WIDTH - 1 downto 0);
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signal btc_wr_addr : std_ulogic_vector(BTC_ADDR_BITS - 1 downto 0);
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begin
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btc_wr_data <= w_in.br_taken &
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r.virt_mode &
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w_in.br_nia(63 downto BTC_ADDR_BITS + 2) &
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w_in.redirect_nia(63 downto 2);
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btc_wr_addr <= w_in.br_nia(BTC_ADDR_BITS + 1 downto 2);
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btc_wr <= w_in.br_last;
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btc_ram : process(clk)
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variable raddr : unsigned(BTC_ADDR_BITS - 1 downto 0);
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begin
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if rising_edge(clk) then
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if advance_nia = '1' then
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if is_X(btc_rd_addr) then
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btc_rd_data <= (others => 'X');
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btc_rd_valid <= 'X';
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else
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btc_rd_data <= btc_memory(to_integer(btc_rd_addr));
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btc_rd_valid <= btc_valids(to_integer(btc_rd_addr));
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end if;
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end if;
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if btc_wr = '1' then
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assert not is_X(btc_wr_addr) report "Writing to unknown address" severity FAILURE;
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btc_memory(to_integer(unsigned(btc_wr_addr))) <= btc_wr_data;
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end if;
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if inval_btc = '1' or rst = '1' then
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btc_valids <= (others => '0');
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elsif btc_wr = '1' then
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assert not is_X(btc_wr_addr) report "Writing to unknown address" severity FAILURE;
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btc_valids(to_integer(unsigned(btc_wr_addr))) <= '1';
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end if;
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end if;
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end process;
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end generate;
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erat_sync : process(clk)
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begin
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if rising_edge(clk) then
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if rst /= '0' or m_in.tlbie = '1' then
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erat.valid <= "00";
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erat.mru <= '0';
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else
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if erat_hit = '1' then
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erat.mru <= erat_sel;
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end if;
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if m_in.tlbld = '1' then
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erat.epn0 <= m_in.addr(63 downto MIN_LG_PGSZ);
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erat.rpn0 <= m_in.pte(REAL_ADDR_BITS-1 downto MIN_LG_PGSZ);
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erat.priv0 <= m_in.pte(3);
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erat.valid(0) <= '1';
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erat.valid(1) <= '0';
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erat.mru <= '0';
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elsif r_int.tlbcheck = '1' and itlb_hit = '1' then
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if erat.mru = '0' then
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erat.epn1 <= r.nia(63 downto MIN_LG_PGSZ);
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erat.rpn1 <= itlb_pte(REAL_ADDR_BITS-1 downto MIN_LG_PGSZ);
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erat.priv1 <= itlb_pte(3);
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erat.valid(1) <= '1';
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else
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erat.epn0 <= r.nia(63 downto MIN_LG_PGSZ);
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erat.rpn0 <= itlb_pte(REAL_ADDR_BITS-1 downto MIN_LG_PGSZ);
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erat.priv0 <= itlb_pte(3);
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erat.valid(0) <= '1';
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end if;
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erat.mru <= not erat.mru;
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end if;
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end if;
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end if;
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end process;
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-- Read TLB using the NIA for the next cycle
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itlb_read : process(clk)
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variable tlb_req_index : std_ulogic_vector(TLB_BITS - 1 downto 0);
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begin
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if rising_edge(clk) then
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if advance_nia = '1' then
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tlb_req_index := hash_ea(r_next.nia);
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if is_X(tlb_req_index) then
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itlb_pte <= (others => 'X');
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itlb_ttag <= (others => 'X');
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itlb_valid <= 'X';
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else
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itlb_pte <= itlb_ptes(to_integer(unsigned(tlb_req_index)));
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itlb_ttag <= itlb_tags(to_integer(unsigned(tlb_req_index)));
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itlb_valid <= itlb_valids(to_integer(unsigned(tlb_req_index)));
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end if;
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end if;
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end if;
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end process;
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-- TLB hit detection
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itlb_lookup : process(all)
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begin
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itlb_hit <= '0';
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if itlb_ttag = r.nia(63 downto MIN_LG_PGSZ + TLB_BITS) then
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itlb_hit <= itlb_valid;
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end if;
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end process;
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-- iTLB update
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itlb_update: process(clk)
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variable wr_index : std_ulogic_vector(TLB_BITS - 1 downto 0);
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begin
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if rising_edge(clk) then
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wr_index := hash_ea(m_in.addr);
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if rst = '1' or (m_in.tlbie = '1' and m_in.doall = '1') then
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-- clear all valid bits
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for i in tlb_index_t loop
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itlb_valids(i) <= '0';
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end loop;
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elsif m_in.tlbie = '1' then
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assert not is_X(wr_index) report "icache index invalid on write" severity FAILURE;
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-- clear entry regardless of hit or miss
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itlb_valids(to_integer(unsigned(wr_index))) <= '0';
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elsif m_in.tlbld = '1' then
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assert not is_X(wr_index) report "icache index invalid on write" severity FAILURE;
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itlb_tags(to_integer(unsigned(wr_index))) <= m_in.addr(63 downto MIN_LG_PGSZ + TLB_BITS);
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itlb_ptes(to_integer(unsigned(wr_index))) <= m_in.pte;
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itlb_valids(to_integer(unsigned(wr_index))) <= '1';
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end if;
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--ev.itlb_miss_resolved <= m_in.tlbld and not rst;
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end if;
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end process;
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comb : process(all)
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variable v : Fetch1ToIcacheType;
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variable v_int : reg_internal_t;
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variable next_nia : std_ulogic_vector(63 downto 0);
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variable m32 : std_ulogic;
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variable ehit, esel : std_ulogic;
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variable eaa_priv : std_ulogic;
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begin
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v := r;
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v_int := r_int;
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v.predicted := '0';
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v.pred_ntaken := '0';
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v.req := not stop_in;
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v_int.tlbstall := r_int.tlbcheck;
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v_int.tlbcheck := '0';
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if r_int.tlbcheck = '1' and itlb_hit = '0' then
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v.fetch_fail := '1';
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end if;
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-- Combinatorial computation of the CIA for the next cycle.
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-- Needs to be simple so the result can be used for RAM
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-- and TLB access in the icache.
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-- If we are stalled, this still advances, and the assumption
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-- is that it will not be used.
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m32 := r_int.mode_32bit;
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if w_in.redirect = '1' then
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next_nia := w_in.redirect_nia(63 downto 2) & "00";
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m32 := w_in.mode_32bit;
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v.virt_mode := w_in.virt_mode;
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v.priv_mode := w_in.priv_mode;
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v.big_endian := w_in.big_endian;
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v_int.mode_32bit := w_in.mode_32bit;
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v.fetch_fail := '0';
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elsif d_in.redirect = '1' then
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next_nia := d_in.redirect_nia(63 downto 2) & "00";
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v.fetch_fail := '0';
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elsif r_int.tlbstall = '1' then
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-- this case is needed so that the correct icache tags are read
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next_nia := r.nia;
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else
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next_nia := r_int.next_nia;
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end if;
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if m32 = '1' then
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next_nia(63 downto 32) := (others => '0');
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end if;
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v.nia := next_nia;
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v_int.next_nia := std_ulogic_vector(unsigned(next_nia) + 4);
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-- Use v_int.next_nia as the BTC read address before it gets possibly
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-- overridden with the reset or interrupt address or the predicted branch
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-- target address, in order to improve timing. If it gets overridden then
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-- rd_is_niap4 gets cleared to indicate that the BTC data doesn't apply.
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btc_rd_addr <= unsigned(v_int.next_nia(BTC_ADDR_BITS + 1 downto 2));
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v_int.rd_is_niap4 := '1';
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-- If the last NIA value went down with a stop mark, it didn't get
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-- executed, and hence we shouldn't increment NIA.
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advance_nia <= rst or w_in.interrupt or w_in.redirect or d_in.redirect or
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(not r.stop_mark and not (r.req and stall_in));
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-- reduce metavalue warnings in sim
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if is_X(rst) then
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advance_nia <= '1';
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end if;
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-- Translate next_nia to real if possible, otherwise we have to stall
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-- and look up the TLB.
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ehit := '0';
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esel := '0';
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eaa_priv := '1';
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if next_nia(63 downto MIN_LG_PGSZ) = erat.epn1 and erat.valid(1) = '1' then
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ehit := '1';
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esel := '1';
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end if;
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if next_nia(63 downto MIN_LG_PGSZ) = erat.epn0 and erat.valid(0) = '1' then
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ehit := '1';
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end if;
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if v.virt_mode = '0' then
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v.rpn := v.nia(REAL_ADDR_BITS - 1 downto MIN_LG_PGSZ);
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eaa_priv := '1';
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elsif esel = '1' then
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v.rpn := erat.rpn1;
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eaa_priv := erat.priv1;
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else
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v.rpn := erat.rpn0;
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eaa_priv := erat.priv0;
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end if;
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if advance_nia = '1' and ehit = '0' and v.virt_mode = '1' and
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r_int.tlbcheck = '0' and v.fetch_fail = '0' then
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v_int.tlbstall := '1';
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v_int.tlbcheck := '1';
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end if;
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if ehit = '1' or v.virt_mode = '0' then
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if eaa_priv = '1' and v.priv_mode = '0' then
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v.fetch_fail := '1';
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else
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v.fetch_fail := '0';
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end if;
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end if;
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erat_hit <= ehit and advance_nia;
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erat_sel <= esel;
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if rst /= '0' then
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if alt_reset_in = '1' then
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v_int.next_nia := ALT_RESET_ADDRESS;
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else
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v_int.next_nia := RESET_ADDRESS;
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end if;
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elsif w_in.interrupt = '1' then
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v_int.next_nia := 52x"0" & w_in.intr_vec(11 downto 2) & "00";
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end if;
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if rst /= '0' or w_in.interrupt = '1' then
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v.req := '0';
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v.virt_mode := '0';
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v.priv_mode := '1';
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v.big_endian := '0';
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v_int.mode_32bit := '0';
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v_int.rd_is_niap4 := '0';
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v_int.tlbstall := '0';
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v_int.tlbcheck := '0';
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v.fetch_fail := '0';
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end if;
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if v.fetch_fail = '1' then
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v_int.tlbstall := '1';
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end if;
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if v_int.tlbstall = '1' then
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v.req := '0';
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end if;
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-- If there is a valid entry in the BTC which corresponds to the next instruction,
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-- use that to predict the address of the instruction after that.
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-- (w_in.redirect = '0' and d_in.redirect = '0' and r_int.tlbstall = '0')
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-- implies v.nia = r_int.next_nia.
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-- r_int.rd_is_niap4 implies r_int.next_nia is the address used to read the BTC.
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if v.req = '1' and w_in.redirect = '0' and d_in.redirect = '0' and r_int.tlbstall = '0' and
|
|
btc_rd_valid = '1' and r_int.rd_is_niap4 = '1' and
|
|
btc_rd_data(BTC_WIDTH - 2) = r.virt_mode and
|
|
btc_rd_data(BTC_WIDTH - 3 downto BTC_TARGET_BITS)
|
|
= r_int.next_nia(BTC_TAG_BITS + BTC_ADDR_BITS + 1 downto BTC_ADDR_BITS + 2) then
|
|
v.predicted := btc_rd_data(BTC_WIDTH - 1);
|
|
v.pred_ntaken := not btc_rd_data(BTC_WIDTH - 1);
|
|
if btc_rd_data(BTC_WIDTH - 1) = '1' then
|
|
v_int.next_nia := btc_rd_data(BTC_TARGET_BITS - 1 downto 0) & "00";
|
|
v_int.rd_is_niap4 := '0';
|
|
end if;
|
|
end if;
|
|
|
|
r_next <= v;
|
|
r_next_int <= v_int;
|
|
|
|
-- Update outputs to the icache
|
|
i_out <= r;
|
|
i_out.next_nia <= next_nia;
|
|
i_out.next_rpn <= v.rpn;
|
|
|
|
end process;
|
|
|
|
end architecture behaviour;
|