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422 lines
16 KiB
Plaintext
422 lines
16 KiB
Plaintext
################################################################################
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# clkin, reset, uart pins...
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################################################################################
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set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports ext_clk]
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set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports ext_rst_n]
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set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports uart_main_tx]
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set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports uart_main_rx]
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################################################################################
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# Pmod Header JC: UART (bottom)
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################################################################################
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#set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_cts_n }];
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#set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_tx }];
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#set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rx }];
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#set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rts_n }];
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################################################################################
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# LEDs
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################################################################################
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set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS25 } [get_ports { led0 }];
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set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS25 } [get_ports { led1 }];
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set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS25 } [get_ports { led2 }];
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set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS25 } [get_ports { led3 }];
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set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS25 } [get_ports { led4 }];
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set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS25 } [get_ports { led5 }];
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set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS25 } [get_ports { led6 }];
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set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS25 } [get_ports { led7 }];
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################################################################################
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# SPI Flash
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################################################################################
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set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_cs_n }];
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set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_mosi }];
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set_property -dict { PACKAGE_PIN R22 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_miso }];
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set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_wp_n }];
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set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_hold_n }];
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################################################################################
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# SD card
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################################################################################
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set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_clk }]
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set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sdcard_cd }]
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set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_cmd }]
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set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[0] }]
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set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[1] }]
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set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[2] }]
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set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 SLEW FAST } [get_ports { sdcard_data[3] }]
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set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { sdcard_reset }]
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# Put registers into IOBs to improve timing
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set_property IOB true [get_cells -hierarchical -filter {NAME =~*.litesdcard/sdcard_*}]
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################################################################################
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# Ethernet (generated by LiteX)
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################################################################################
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# eth_clocks:0.tx
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set_property LOC AA14 [get_ports {eth_clocks_tx}]
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set_property IOSTANDARD LVCMOS25 [get_ports {eth_clocks_tx}]
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# eth_clocks:0.rx
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set_property LOC V13 [get_ports {eth_clocks_rx}]
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set_property IOSTANDARD LVCMOS25 [get_ports {eth_clocks_rx}]
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# eth:0.rst_n
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set_property LOC U7 [get_ports {eth_rst_n}]
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set_property IOSTANDARD LVCMOS25 [get_ports {eth_rst_n}]
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set_property IOSTANDARD LVCMOS33 [get_ports {eth_rst_n}]
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# eth:0.int_n
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set_property LOC Y14 [get_ports {eth_int_n}]
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set_property IOSTANDARD LVCMOS25 [get_ports {eth_int_n}]
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# eth:0.mdio
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set_property LOC Y16 [get_ports {eth_mdio}]
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set_property IOSTANDARD LVCMOS25 [get_ports {eth_mdio}]
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# eth:0.mdc
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set_property LOC AA16 [get_ports {eth_mdc}]
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set_property IOSTANDARD LVCMOS25 [get_ports {eth_mdc}]
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# eth:0.rx_ctl
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set_property LOC W10 [get_ports {eth_rx_ctl}]
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set_property IOSTANDARD LVCMOS25 [get_ports {eth_rx_ctl}]
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# eth:0.rx_data
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set_property LOC AB16 [get_ports {eth_rx_data[0]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {eth_rx_data[0]}]
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# eth:0.rx_data
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set_property LOC AA15 [get_ports {eth_rx_data[1]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {eth_rx_data[1]}]
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# eth:0.rx_data
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set_property LOC AB15 [get_ports {eth_rx_data[2]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {eth_rx_data[2]}]
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# eth:0.rx_data
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set_property LOC AB11 [get_ports {eth_rx_data[3]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {eth_rx_data[3]}]
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# eth:0.tx_ctl
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set_property LOC V10 [get_ports {eth_tx_ctl}]
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set_property IOSTANDARD LVCMOS25 [get_ports {eth_tx_ctl}]
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# eth:0.tx_data
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set_property LOC Y12 [get_ports {eth_tx_data[0]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {eth_tx_data[0]}]
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# eth:0.tx_data
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set_property LOC W12 [get_ports {eth_tx_data[1]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {eth_tx_data[1]}]
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# eth:0.tx_data
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set_property LOC W11 [get_ports {eth_tx_data[2]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {eth_tx_data[2]}]
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# eth:0.tx_data
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set_property LOC Y11 [get_ports {eth_tx_data[3]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {eth_tx_data[3]}]
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################################################################################
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# DRAM (generated by LiteX)
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################################################################################
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# ddram:0.a
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set_property LOC M2 [get_ports {ddram_a[0]}]
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set_property SLEW FAST [get_ports {ddram_a[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[0]}]
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# ddram:0.a
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set_property LOC M5 [get_ports {ddram_a[1]}]
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set_property SLEW FAST [get_ports {ddram_a[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[1]}]
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# ddram:0.a
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set_property LOC M3 [get_ports {ddram_a[2]}]
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set_property SLEW FAST [get_ports {ddram_a[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[2]}]
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# ddram:0.a
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set_property LOC M1 [get_ports {ddram_a[3]}]
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set_property SLEW FAST [get_ports {ddram_a[3]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[3]}]
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# ddram:0.a
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set_property LOC L6 [get_ports {ddram_a[4]}]
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set_property SLEW FAST [get_ports {ddram_a[4]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[4]}]
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# ddram:0.a
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set_property LOC P1 [get_ports {ddram_a[5]}]
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set_property SLEW FAST [get_ports {ddram_a[5]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[5]}]
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# ddram:0.a
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set_property LOC N3 [get_ports {ddram_a[6]}]
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set_property SLEW FAST [get_ports {ddram_a[6]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[6]}]
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# ddram:0.a
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set_property LOC N2 [get_ports {ddram_a[7]}]
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set_property SLEW FAST [get_ports {ddram_a[7]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[7]}]
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# ddram:0.a
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set_property LOC M6 [get_ports {ddram_a[8]}]
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set_property SLEW FAST [get_ports {ddram_a[8]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[8]}]
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# ddram:0.a
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set_property LOC R1 [get_ports {ddram_a[9]}]
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set_property SLEW FAST [get_ports {ddram_a[9]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[9]}]
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# ddram:0.a
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set_property LOC L5 [get_ports {ddram_a[10]}]
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set_property SLEW FAST [get_ports {ddram_a[10]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[10]}]
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# ddram:0.a
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set_property LOC N5 [get_ports {ddram_a[11]}]
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set_property SLEW FAST [get_ports {ddram_a[11]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[11]}]
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# ddram:0.a
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set_property LOC N4 [get_ports {ddram_a[12]}]
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set_property SLEW FAST [get_ports {ddram_a[12]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[12]}]
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# ddram:0.a
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set_property LOC P2 [get_ports {ddram_a[13]}]
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set_property SLEW FAST [get_ports {ddram_a[13]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[13]}]
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# ddram:0.a
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set_property LOC P6 [get_ports {ddram_a[14]}]
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set_property SLEW FAST [get_ports {ddram_a[14]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_a[14]}]
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# ddram:0.ba
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set_property LOC L3 [get_ports {ddram_ba[0]}]
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set_property SLEW FAST [get_ports {ddram_ba[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[0]}]
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# ddram:0.ba
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set_property LOC K6 [get_ports {ddram_ba[1]}]
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set_property SLEW FAST [get_ports {ddram_ba[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[1]}]
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# ddram:0.ba
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set_property LOC L4 [get_ports {ddram_ba[2]}]
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set_property SLEW FAST [get_ports {ddram_ba[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[2]}]
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# ddram:0.ras_n
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set_property LOC J4 [get_ports {ddram_ras_n}]
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set_property SLEW FAST [get_ports {ddram_ras_n}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_ras_n}]
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# ddram:0.cas_n
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set_property LOC K3 [get_ports {ddram_cas_n}]
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set_property SLEW FAST [get_ports {ddram_cas_n}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_cas_n}]
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# ddram:0.we_n
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set_property LOC L1 [get_ports {ddram_we_n}]
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set_property SLEW FAST [get_ports {ddram_we_n}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_we_n}]
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# ddram:0.dm
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set_property LOC G3 [get_ports {ddram_dm[0]}]
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set_property SLEW FAST [get_ports {ddram_dm[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[0]}]
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# ddram:0.dm
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set_property LOC F1 [get_ports {ddram_dm[1]}]
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set_property SLEW FAST [get_ports {ddram_dm[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[1]}]
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# ddram:0.dq
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set_property LOC G2 [get_ports {ddram_dq[0]}]
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set_property SLEW FAST [get_ports {ddram_dq[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[0]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[0]}]
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# ddram:0.dq
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set_property LOC H4 [get_ports {ddram_dq[1]}]
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set_property SLEW FAST [get_ports {ddram_dq[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[1]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[1]}]
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# ddram:0.dq
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set_property LOC H5 [get_ports {ddram_dq[2]}]
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set_property SLEW FAST [get_ports {ddram_dq[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[2]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[2]}]
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# ddram:0.dq
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set_property LOC J1 [get_ports {ddram_dq[3]}]
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set_property SLEW FAST [get_ports {ddram_dq[3]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[3]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[3]}]
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# ddram:0.dq
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set_property LOC K1 [get_ports {ddram_dq[4]}]
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set_property SLEW FAST [get_ports {ddram_dq[4]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[4]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[4]}]
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# ddram:0.dq
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set_property LOC H3 [get_ports {ddram_dq[5]}]
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set_property SLEW FAST [get_ports {ddram_dq[5]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[5]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[5]}]
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# ddram:0.dq
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set_property LOC H2 [get_ports {ddram_dq[6]}]
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set_property SLEW FAST [get_ports {ddram_dq[6]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[6]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[6]}]
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# ddram:0.dq
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set_property LOC J5 [get_ports {ddram_dq[7]}]
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set_property SLEW FAST [get_ports {ddram_dq[7]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[7]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[7]}]
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# ddram:0.dq
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set_property LOC E3 [get_ports {ddram_dq[8]}]
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set_property SLEW FAST [get_ports {ddram_dq[8]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[8]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[8]}]
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# ddram:0.dq
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set_property LOC B2 [get_ports {ddram_dq[9]}]
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set_property SLEW FAST [get_ports {ddram_dq[9]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[9]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[9]}]
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# ddram:0.dq
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set_property LOC F3 [get_ports {ddram_dq[10]}]
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set_property SLEW FAST [get_ports {ddram_dq[10]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[10]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[10]}]
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# ddram:0.dq
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set_property LOC D2 [get_ports {ddram_dq[11]}]
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set_property SLEW FAST [get_ports {ddram_dq[11]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[11]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[11]}]
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# ddram:0.dq
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set_property LOC C2 [get_ports {ddram_dq[12]}]
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set_property SLEW FAST [get_ports {ddram_dq[12]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[12]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[12]}]
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# ddram:0.dq
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set_property LOC A1 [get_ports {ddram_dq[13]}]
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set_property SLEW FAST [get_ports {ddram_dq[13]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[13]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[13]}]
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# ddram:0.dq
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set_property LOC E2 [get_ports {ddram_dq[14]}]
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set_property SLEW FAST [get_ports {ddram_dq[14]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[14]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[14]}]
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# ddram:0.dq
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set_property LOC B1 [get_ports {ddram_dq[15]}]
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set_property SLEW FAST [get_ports {ddram_dq[15]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[15]}]
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set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[15]}]
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# ddram:0.dqs_p
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set_property LOC K2 [get_ports {ddram_dqs_p[0]}]
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set_property SLEW FAST [get_ports {ddram_dqs_p[0]}]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[0]}]
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# ddram:0.dqs_p
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set_property LOC E1 [get_ports {ddram_dqs_p[1]}]
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set_property SLEW FAST [get_ports {ddram_dqs_p[1]}]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[1]}]
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# ddram:0.dqs_n
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set_property LOC J2 [get_ports {ddram_dqs_n[0]}]
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set_property SLEW FAST [get_ports {ddram_dqs_n[0]}]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[0]}]
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# ddram:0.dqs_n
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set_property LOC D1 [get_ports {ddram_dqs_n[1]}]
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set_property SLEW FAST [get_ports {ddram_dqs_n[1]}]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[1]}]
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# ddram:0.clk_p
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set_property LOC P5 [get_ports {ddram_clk_p}]
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set_property SLEW FAST [get_ports {ddram_clk_p}]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_p}]
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# ddram:0.clk_n
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set_property LOC P4 [get_ports {ddram_clk_n}]
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set_property SLEW FAST [get_ports {ddram_clk_n}]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_n}]
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# ddram:0.cke
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set_property LOC J6 [get_ports {ddram_cke}]
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set_property SLEW FAST [get_ports {ddram_cke}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_cke}]
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# ddram:0.odt
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set_property LOC K4 [get_ports {ddram_odt}]
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set_property SLEW FAST [get_ports {ddram_odt}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_odt}]
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# ddram:0.reset_n
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set_property LOC G1 [get_ports {ddram_reset_n}]
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set_property SLEW FAST [get_ports {ddram_reset_n}]
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set_property IOSTANDARD SSTL15 [get_ports {ddram_reset_n}]
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################################################################################
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# Design constraints and bitsteam attributes
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################################################################################
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#Internal VREF
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set_property INTERNAL_VREF 0.750 [get_iobanks 35]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property CFGBVS VCCO [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
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set_property CONFIG_MODE SPIx4 [current_design]
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|
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################################################################################
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# Clock constraints
|
|
################################################################################
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create_clock -name sys_clk_pin -period 10.00 [get_ports { ext_clk }];
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create_clock -name eth_clocks_rx -period 8.0 [get_ports { eth_clocks_rx }]
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set_clock_groups -asynchronous -group [get_clocks sys_clk_pin -include_generated_clocks] -group [get_clocks eth_clocks_rx -include_generated_clocks]
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################################################################################
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# False path constraints (from LiteX as they relate to LiteDRAM and LiteEth)
|
|
################################################################################
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|
set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}]
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set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
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|
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|
set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]]
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