A tiny Open POWER ISA softcore written in VHDL 2008
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library ieee; |
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use ieee.std_logic_1164.all; |
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library work; |
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package git is |
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constant GIT_HASH : std_ulogic_vector(55 downto 0) := x"@hash@"; |
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constant GIT_DIRTY : std_ulogic := '@dirty@'; |
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end git;
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